Simon Atanasyan
c5e99819f4
[Mips] Adjust float ABI settings in case of MIPS16 mode.
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Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).
The patch reviewed by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 12:20:17 +00:00
Reed Kotler
b359bda93d
Let rotr and bswap be handled by expansion for Mips16 since we don't
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have native instructions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 17:32:33 +00:00
Akira Hatanaka
ed2a7d2780
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
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tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:08:41 +00:00
Akira Hatanaka
5773fd52ef
Remove unnecessary checking of register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 19:18:24 +00:00
Bruno Cardoso Lopes
908b6ddad6
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 17:32:30 +00:00
