A TableGen backend can define how certain classes can be expanded into
ordered sets of defs, typically by evaluating a specific field in the
record. The SetTheory class can then evaluate DAG expressions that refer
to these named sets.
A number of standard set and list operations are predefined, and the
backend can add more specialized operators if needed. The -print-sets
backend is used by SetTheory.td to provide examples.
This is intended to simplify how register classes are defined:
def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
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class A<bit a, bits<3> x, bits<3> y> {
bits<3> z;
let z = !if(a, x, y);
}
The variable z will get the value of x when 'a' is 1 and 'y' when a is '0'.
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as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
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Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
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Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
(mem_frag addr:$src2))))];
The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
(mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
(mem_frag addr:$src2))))];
Fix this by passing the right name when creating a new DagInit node.
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If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.
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of runs without leak checking. We add -vg to the triple for non-checked runs,
or -vg_leak for checked runs. Also use this to XFAIL the TableGen tests, since
tablegen leaks like a sieve. This includes some valgrindArgs refactoring.
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values, resolving references to them, and then removing the definitions.
If a template argument is set to an undefined value, we need to resolve
references to that argument to an explicit undefined value. The current code
leaves the reference to the template argument as it is, which causes an
assertion failure later when the definition of the template argument is
removed.
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other operators. For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.
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Use it on dags and lists like this:
class decls {
string name;
}
def Decls : decls;
class B<list<string> names> : A<!foreach(Decls.name, names, !strconcat(Decls.name, ", Sr."))>;
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#NAME# with the name of the defm instantiating the multiclass. This is
useful for AVX instruction naming where a "V" prefix is standard
throughout the ISA. For example:
multiclass SSE_AVX_Inst<...> {
def SS : Instr<...>;
def SD : Instr<...>;
def PS : Instr<...>;
def PD : Instr<...>;
def V#NAME#SS : Instr<...>;
def V#NAME#SD : Instr<...>;
def V#NAME#PS : Instr<...>;
def V#NAME#PD : Instr<...>;
}
defm ADD : SSE_AVX_Inst<...>;
Results in
ADDSS
ADDSD
ADDPS
ADDPD
VADDSS
VADDSD
VADDPS
VADDPD
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by base multiclasses. Do not attempt to alter defs from previous base
multiclasses. This fixes multiple multiclass inheritance.
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use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
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