6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity
60,331 Commits 39 Branches 0 Tags 277 MiB
4781e30b7b
Commit Graph

14559 Commits

Author SHA1 Message Date
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Dan Gohman
acbfc157d2 Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 22:38:11 +00:00
Dan Gohman
3335a22a37 Make this code less confusing. Instead of reassigning BB, just operate 
on the original variables, so it's easier to see what is being done
to which blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 20:14:26 +00:00
Dan Gohman
71edb241a1 Remove the -disable-16bit command-line option, which is now obsolete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 18:30:26 +00:00
Evan Cheng
1361796dd0 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 01:12:32 +00:00
Dan Gohman
ffce6f1343 Don't leave Base.FrameIndex uninitialized, so that it doesn't 
print randomly in debug output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 23:30:41 +00:00
Dale Johannesen
8c5358c936 Make naked functions work on PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 19:32:19 +00:00
Devang Patel
67a444ca36 Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g. 
##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 18:52:10 +00:00
Evan Cheng
3f54c64a98 Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 05:08:22 +00:00
Mon P Wang
b9a01bcf48 Add support for assemblers that don't support periods in a name 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 04:00:56 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Kevin Enderby
9ac7282117 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the 
Operand size override prefix to be part of their records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 23:20:40 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Jakob Stoklund Olesen
7261fb2a6f Teach X86FloatingPoint that a register can be killed multiple times by the same 
instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 18:28:37 +00:00
Evan Cheng
2bce5f4b56 Enable i16 to i32 promotion by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 08:30:49 +00:00
Evan Cheng
39cfeecae5 Unbreak the build. Only form shld / shrd after legalization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 02:25:18 +00:00
Devang Patel
28ff35d030 Emit debug info for byval parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:39:28 +00:00
Evan Cheng
8b1190a540 Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:18:01 +00:00
Chris Lattner
a7b611c10d further simplify EmitAlignment by eliminating the 
ForcedAlignBits argument, tweaking the single client of it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:08:40 +00:00
Stuart Hastings
5a6a65be46 Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 00:35:10 +00:00
Devang Patel
a00adba6a7 Use MachineOperand::is* predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102472 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 22:24:37 +00:00
Evan Cheng
1c45acf510 Fix obvious typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 21:46:03 +00:00
Evan Cheng
b3716e3e28 SRA promotion is also not free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 19:48:31 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:37:21 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Dale Johannesen
efc3a6348a Add PPC AsmPrinter handling for target-specific form of 
DBG_VALUE, and a cautionary comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:05:01 +00:00
Evan Cheng
552f09a0d7 Promoting 16-bit cmp / test aren't free. Don't do it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 19:06:11 +00:00
Evan Cheng
fc4d530ad6 Remove a redundant comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 08:16:57 +00:00
Evan Cheng
0965217e74 Add PPC specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:36 +00:00
Evan Cheng
62b50656ce Add ARM specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:25 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. 
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af Stop abusing EmitInstrWithCustomInserter for target-dependent 
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-25 21:33:54 +00:00
Evan Cheng
c82c20b315 Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-24 04:44:57 +00:00
Dan Gohman
6e8fd90602 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:41:15 +00:00
Stuart Hastings
e3ff9ba40c Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:03:32 +00:00
Evan Cheng
2808ccb775 Fix X86ISD::CMP i16 to i32 promotion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 18:21:16 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00
Dan Gohman
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:46:50 +00:00
Evan Cheng
07c4e1085d - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:19:46 +00:00
Johnny Chen
c048f1d12c Modified some assert() msg strings; no other functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Evan Cheng
5528e7bcb1 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:47:12 +00:00
Evan Cheng
fe5dcbc27d Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:39:06 +00:00
Dan Gohman
f0757b0edc Add more const qualifiers on TargetMachine and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:34:56 +00:00
Johnny Chen
52d2b0ed00 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:01:19 +00:00
Bill Wendling
a040fffefb Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 00:34:04 +00:00
Chris Lattner
d6139425f5 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 23:18:40 +00:00
Dale Johannesen
7609017dc3 Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 22:34:09 +00:00
Johnny Chen
d6b5d72c0f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 21:29:28 +00:00