Commit Graph

9 Commits

Author SHA1 Message Date
Dan Gohman
74f6f9a931 Enable the new no-SP register classes by default. This is to address
PR4572. A few tests have some minor code regressions due to different
coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 17:40:24 +00:00
Dan Gohman
40a0b2c305 Revert changes accidentally committed along with r78163.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78165 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 05:38:13 +00:00
Dan Gohman
c3c9c486e4 Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
MMX arguments. This fixes PR4684.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 05:33:42 +00:00
Jakob Stoklund Olesen
ded2e3b0d0 LowerSubregsInstructionPass::LowerExtract should not extend the live range of registers.
When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the
kill flag to the place where the sub-register is killed. This can accidentally
overlap with the use of a sibling sub-register, and we have trouble.

In the test case we have this code:

Live Ins: %R0 %R1 %R2
	%R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
	%R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
	%R1L<def> = EXTRACT_SUBREG %R1<kill>, 1
	%R0L<def> = EXTRACT_SUBREG %R0<kill>, 1
	%R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>

subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: eliminated!
subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>

The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H:

*** Bad machine code: Redefining a live physical register ***
- function:    f
- basic block:  0x18358c0 (#0)
- instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
Register R2H was defined but already live.

The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating
it completely:

subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill>

Note that these IMPLICIT_DEF instructions survive to the asm output. It is
necessary to fix the stack-color-with-reg test case because of that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78093 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 20:01:11 +00:00
Evan Cheng
438d9900c0 Catch more coalescing opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76282 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 04:52:23 +00:00
Evan Cheng
5248468473 Enable cross register class coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 02:10:10 +00:00
Evan Cheng
1ea7327845 Fixed a stack slot coloring with reg bug: do not update implicit use / def when doing forward / backward propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 18:31:57 +00:00
Bill Wendling
d0c1f9c932 Temporarily revert r71010. It was causing massive failures during self-hosting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-07 01:27:25 +00:00
Evan Cheng
f9a9b51429 Enable stack coloring with regs at -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71010 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 20:30:36 +00:00