Commit Graph

5 Commits

Author SHA1 Message Date
Tim Northover
ca396e391e IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 10:48:52 +00:00
Jakob Stoklund Olesen
17ca0f8f80 Implement SPARCv9 atomic_swap_64 with a pseudo.
The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:48:46 +00:00
Jakob Stoklund Olesen
06626a6924 Fix swapped CASA operands.
Found by SingleSource/UnitTests/AtomicOps.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200130 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:09:54 +00:00
Jakob Stoklund Olesen
c30791627e Implement atomicrmw operations in 32 and 64 bits for SPARCv9.
These all use the compare-and-swap CASA/CASXA instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199975 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 06:23:31 +00:00
Venkatraman Govindaraju
447c3480e5 [Sparc] Handle atomic loads/stores in sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 22:11:54 +00:00