Craig Topper
58bbb81764
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
Craig Topper
6b0b2d6c41
Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:39:34 +00:00
Eli Friedman
885f1a0c04
Zap some junk from the ARM instruction descriptions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:29:58 +00:00
Eli Friedman
f73c881f4a
Fix the assembler strings for a couple of atomic instructions. Doesn't really matter much in practice, but it's a bit cleaner.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 00:27:04 +00:00
Jim Grosbach
2d539691a1
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 23:36:42 +00:00
Bruno Cardoso Lopes
5fc48100ee
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:23 +00:00
Owen Anderson
cd00dc6852
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:28:46 +00:00
Bruno Cardoso Lopes
457d53d9ce
Revert the wrong part of r139528, and fix testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Owen Anderson
fd92d2e106
Fix encoding of PC-relative LDRSHW with an immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:36:51 +00:00
Owen Anderson
a073795023
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:07:22 +00:00
Bruno Cardoso Lopes
8e03a821f9
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Bruno Cardoso Lopes
93474f5f7f
Organize a bit the operand names for CMPPS and CMPPD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:36 +00:00
Bruno Cardoso Lopes
cf355422d6
Realign BLEND patterns to match the general style for patterns in .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139526 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:33 +00:00
Bruno Cardoso Lopes
3445df77d4
Fix 80-columns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:29 +00:00
Owen Anderson
a3157b4026
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:56:30 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Richard Osborne
2cb6c1bd20
Mark LDWCP as having no side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:41:31 +00:00
Nadav Rotem
5ed0983200
Format patterns, remove unused X86blend patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 08:41:50 +00:00
Craig Topper
136046c9a2
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
Craig Topper
038197988b
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
Nadav Rotem
fbad25e120
CR fixes per Bruno's request.
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Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 15:02:23 +00:00
Eli Friedman
106f6e7a27
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:01:42 +00:00
Richard Trieu
81cbb0ad60
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
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lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:42:07 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Jim Grosbach
1ad60c2adc
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 00:15:36 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502
Fix an ambiguously nested if.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Akira Hatanaka
46ac94ba8b
O64 will not be supported.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:22:48 +00:00
Akira Hatanaka
5881586745
Make F31 and D15 non-reserved registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:11:26 +00:00
Owen Anderson
51f6a7abf2
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:48:23 +00:00
Akira Hatanaka
9a439affd7
Mips32 does not reserve even-numbered floating point registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:31:46 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d
Thumb2 assembly parsing and encoding for MLA and MLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:24:45 +00:00
Jim Grosbach
0811fe13d6
Thumb2 assembly parsing and encoding for LDRSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:42:40 +00:00
Akira Hatanaka
d199d0c59c
Drop support for Allegrex. Allegrex implements a variant of Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Craig Topper
ccfa4ed4e0
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 05:40:53 +00:00
Akira Hatanaka
ad5f0c9e73
Change default target architecture from Mips1 to Mips32r1 in preparation for
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removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Akira Hatanaka
404507e7d8
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 00:13:35 +00:00
Owen Anderson
441462f932
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:42:49 +00:00
Nadav Rotem
ee64be9c17
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:17:35 +00:00
Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830
Add a AVX version of a simple i64 -> f64 bitcast. This could be
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triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
cbf479df8a
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
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single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:35:57 +00:00
Bruno Cardoso Lopes
814c6ced85
Add AVX versions of blend vector operations and fix some issues noticed
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in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00