Commit Graph

3732 Commits

Author SHA1 Message Date
Reid Kleckner
d7f37d823b Add missing test for r215031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 18:34:54 +00:00
Reid Kleckner
b81e6cf6c5 MC: Diagnose an unexpected token in COFF .section instead of asserting
This can easily arise when trying to assemble and ELF style .section
directive for a COFF object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215373 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 18:34:43 +00:00
Daniel Sanders
e20f611baf Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directives
It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215361 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 16:10:19 +00:00
Daniel Sanders
36cf28e70e [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directives
Patch by Matheus Almeida and Toma Tabacu

Differential Revision: http://reviews.llvm.org/D4179


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-11 15:28:56 +00:00
Joerg Sonnenberger
4417c25b03 @l and friends adjust their value depending the context used in.
For ori, they are unsigned, for addi, signed. Create a new target
expression type to handle this and evaluate Fixups accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215315 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-10 12:41:50 +00:00
Joerg Sonnenberger
06e8dbef25 Allow the third argument for the subi family to be an expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-09 17:10:26 +00:00
Joerg Sonnenberger
0c5a408cf6 Update disassembler test to check the full dccci/iccci form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-09 14:01:10 +00:00
Joerg Sonnenberger
26adfd1ca4 Use the full form of dccci and iccci from the early PPC 405 documents,
since the operands are actually used on those cores. Provide aliases for
the only documented case in the newer Power ISA speec.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-09 13:58:31 +00:00
Joerg Sonnenberger
996a304351 Allow large immediates for branch instructions in 32bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-08 20:57:58 +00:00
Joerg Sonnenberger
c9def6b938 Add support for SPE load/store from memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215220 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-08 16:43:49 +00:00
Joerg Sonnenberger
71c5eed711 Add the majority of the remaining SPE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215131 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 18:52:39 +00:00
Joerg Sonnenberger
39637ed35e Indent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 18:05:32 +00:00
Joerg Sonnenberger
7ad7c75048 Add mfasr and mtasr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 13:35:34 +00:00
Joerg Sonnenberger
d94b6e8895 Add mfrtcu and mfrtcl instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 13:16:58 +00:00
Joerg Sonnenberger
5b1fba4a83 Support mttbl and mttbu mnemonic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 13:06:23 +00:00
Joerg Sonnenberger
80de56ebde Add RFID instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 12:39:59 +00:00
Joerg Sonnenberger
445a9f9729 Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle
predicates properly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 12:18:21 +00:00
Daniel Sanders
6cc2e1a132 [mips] Add assembler support for .set msa/nomsa directive.
Summary:
These directives are used to toggle whether the assembler accepts MSA-specific instructions or not.

Patch by Matheus Almeida and Toma Tabacu.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4783


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215099 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 12:03:36 +00:00
Reid Kleckner
41d6599bb1 MC X86: Accept ".att_syntax prefix" and diagnose noprefix
Fixes PR18916.  I don't think we need to implement support for either
hybrid syntax.  Nobody should write Intel assembly with '%' prefixes on
their registers or AT&T assembly without them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 23:21:13 +00:00
Chad Rosier
4e78deb350 Add test case omitted in r214974.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214975 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 16:06:41 +00:00
Adam Nemet
2b9b50379b [X86] Fixes commit r214890 to match the posted patch
This was another fallout from my local rebase where something went wrong :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 07:13:12 +00:00
Adam Nemet
545f89213d [AVX512] Add masking variant and intrinsics for valignd/q
This is similar to what I did with the two-source permutation recently.  (It's
almost too similar so that we should consider generating the masking variants
with some tablegen help.)

Both encoding and intrinsic tests are added as well.  For the latter, this is
what the IR that the intrinsic test on the clang side generates.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 17:23:04 +00:00
Joerg Sonnenberger
2888b08b44 Add accessors for the PPC 403 bank registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214875 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 15:45:15 +00:00
Renato Golin
84bd563975 Add tests for cp10/cp11 on ARMv5/6
Tests for ARMv7/8 are already on diagnostics.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214872 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 15:29:41 +00:00
Keith Walker
f2115a0b0d Specify that the thumb setend and blx <immed> instructions are not valid on an m-class target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214871 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 15:11:59 +00:00
Keith Walker
966fc9344b Define stc2/stc2l/ldc2/ldc2l as thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 14:58:05 +00:00
Joerg Sonnenberger
bb97134ffe Accessors for SSR2 and SSR3 on PPC 403.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 14:53:05 +00:00
Joerg Sonnenberger
deaa09e169 Add dci/ici instructions for PPC 476 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 14:40:32 +00:00
Joerg Sonnenberger
2bdd960ae3 Add mftblo and mftbhi for PPC 4xx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 14:18:16 +00:00
Joerg Sonnenberger
0f365741f3 Add lswi / stswi for assembler use with a warning to not add patterns
for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 13:34:01 +00:00
Joerg Sonnenberger
e2f9c8d663 Add TCR register access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 23:53:42 +00:00
Joerg Sonnenberger
7c5b978254 Add PPC 603's tlbld and tlbli instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214825 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 23:49:45 +00:00
Kevin Enderby
2a78a0cd47 Enable Darwin vararg parameters support in assembler macros.
Duplicate the vararg tests for linux and add a tests which mixed
vararg arguments with darwin positional parameters.

Patch by: Janne Grunau <j@jannau.net>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214799 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 23:14:37 +00:00
Joerg Sonnenberger
db3ce56a58 Add simplified aliases for access to DCCR, ICCR, DEAR and ESR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 22:56:42 +00:00
Joerg Sonnenberger
25c8b4774b tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:28:22 +00:00
Joerg Sonnenberger
355845b437 Recognize mftbl as alias for mftb, for symmetry with mttb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214769 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 20:28:34 +00:00
Joerg Sonnenberger
e8f23a8a5d Allow .lcomm with alignment on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 18:45:10 +00:00
Joerg Sonnenberger
df64464ad2 Add support for m[ft][di]bat[ul] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214731 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 17:07:41 +00:00
Joerg Sonnenberger
977b978f93 Add features for PPC 4xx and e500/e500mc instructions.
Move the test cases for them into separate files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214724 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 15:47:38 +00:00
Robert Khasanov
7017934668 [SKX] Enabling load/store instructions: encoding
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214719 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 14:35:15 +00:00
Daniel Sanders
98b419bff7 [mips] Add assembler support for '.set mipsX'.
Summary:
This patch also fixes an issue with the way the Mips assembler enables/disables architecture
features. Before this patch, the assembler never disabled feature bits. For example,
.set mips64
.set mips32r2

would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right.
Unfortunately this isn't trivial to fix because there's not an easy way to clear
feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits
that imply the feature being cleared and not the implied bits by the feature (there's a
better explanation to the code I added).

Patch by Matheus Almeida and updated by Toma Tabacu

Reviewers: vmedic, matheusalmeida, dsanders

Reviewed By: dsanders

Subscribers: tomatabacu, llvm-commits

Differential Revision: http://reviews.llvm.org/D4123


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214709 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 12:20:00 +00:00
Joerg Sonnenberger
a0e1d10f75 tlbia support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 20:16:29 +00:00
Joerg Sonnenberger
55f925abc5 mfdcr / mtdcr support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214639 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 20:00:26 +00:00
Joerg Sonnenberger
419f3804f0 Don't use additional arguments for dss and friends to satisfy DSS_Form,
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 15:09:41 +00:00
James Molloy
ea029d5b15 Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back.
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed.

Patch by Petr Pavlu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:42:11 +00:00
Tilmann Scheller
3b3fa38731 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions.
The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:08:04 +00:00
Tilmann Scheller
9bd0d2a6a0 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions.
The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 11:33:47 +00:00
Tilmann Scheller
70c9be77f7 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions.
The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 11:08:51 +00:00
Kevin Enderby
42deb12738 Add support for the X86 secure guard extensions instructions in assembler (SGX).
This allows assembling the two new instructions, encls and enclu for the
SKX processor model.

Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.

rdar://16228228


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:57:38 +00:00
Reid Kleckner
0b3444cca9 X86 MC: Don't crash on empty memory operand parens
Instead, create an absolute memory operand.

Fixes PR20504.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:26:35 +00:00