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5031 Commits

Author SHA1 Message Date
Nadav Rotem
0c3e67860a Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd 
types such as i33 were rounded to i32. Originated from Duncan's testcase.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-12 14:56:55 +00:00
Nadav Rotem
b05f14b3b9 Improve the generated code by getCopyFromPartsVector for promoted integer types. 
Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-12 14:49:38 +00:00
Chad Rosier
8c1ec5a0a2 Revert r132871. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-11 02:27:46 +00:00
Chad Rosier
e4c705667b Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-11 02:16:36 +00:00
Eric Christopher
b3e009a165 80-col cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 23:05:08 +00:00
Eli Friedman
2a6d9eb10b Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809. 
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 22:14:44 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 23:55:35 +00:00
Andrew Trick
8ae3edacfa Remove a temporary test case probe in CheckForLiveRegDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 15:19:49 +00:00
Andrew Trick
9d507aec07 Fix a merge bug in preRAsched for handling physreg aliases. 
I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 00:38:12 +00:00
Nadav Rotem
fc3623bc50 Add methods to support the integer-promotion of vector types. Methods to 
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 20:55:56 +00:00
Stuart Hastings
57f1fde7fc Avoid FGETSIGN of 80-bit types. Fixes PR10085. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 16:44:31 +00:00
Eli Friedman
0b4d96baec PR10077: fix fast-isel of extractvalue of aggregate constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 05:46:34 +00:00
Nadav Rotem
0b66636879 TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 20:58:08 +00:00
Nadav Rotem
f1c025d1d1 TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. 
(only happens when using the -promote-elements option).

The correct legalization order is to first try to promote element. Next, we try
to widen vectors.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132648 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 20:32:01 +00:00
Eric Christopher
e0b42c02f0 Add a TODO about memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 17:21:23 +00:00
Eric Christopher
100c833416 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:16:42 +00:00
Rafael Espindola
251b4a0405 Revert 132424 to fix PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:57:47 +00:00
Jakob Stoklund Olesen
fa226bccaa Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:43:46 +00:00
Stuart Hastings
ec880283b3 Recommit 132404 with fixes. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 21:33:14 +00:00
Eric Christopher
9aaa02a1d2 Allow bitcasts between valid types of the same size and vector 
types if the vector type is legal.

Fixes rdar://9306086


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:55:10 +00:00
Nadav Rotem
96e0c5477c Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use 
the TargetLowering enum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132418 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:47:10 +00:00
Stuart Hastings
090bf19de6 Fix double FGETSIGN to work on x86_32; followup to 132396. 
rdar://problem/5660695


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:32:25 +00:00
Stuart Hastings
bdce3726e2 Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132396 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 14:04:17 +00:00
Nadav Rotem
b6fbec3a54 This patch is another step in the direction of adding vector select. In this 
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization.  This flag will be removed when the transition is
complete.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 12:51:46 +00:00
Nadav Rotem
b6aacae941 Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. 
This patch does not change the behavior of the type legalizer. The codegen
produces the same code.
This infrastructural change is needed in order to enable complex decisions
for vector types (needed by the vector-select patch).




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 17:57:14 +00:00
Nadav Rotem
2d6dcb34b7 Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' 
code in one place. Re-apply 131534 and fix the multi-step promotion of integers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 21:03:13 +00:00
Eli Friedman
76927d7303 Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 23:49:02 +00:00
Devang Patel
8a115d5bf4 Remove unused statistical counter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132087 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:55:40 +00:00
Devang Patel
8ec0c1c07b Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 18:27:52 +00:00
Evan Cheng
b5a55d979c - Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is 
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
  when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.

rdar://9490949


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 01:48:22 +00:00
Devang Patel
9728ea2447 Revert 121907 (it causes llc crash) and apply original patch from PR9817. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 22:04:42 +00:00
Devang Patel
233857537f Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function. 
Patch by Micah Villmow


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131908 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 17:44:13 +00:00
Devang Patel
35b6994608 While replacing all uses of a SDValue with another value, do not forget to transfer SDDbgValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131907 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 17:35:08 +00:00
Chris Lattner
9db20f3bd8 Eliminate some temporary variables, and don't call getByValTypeAlignment 
when we're just going to throw the result away.  No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 23:23:02 +00:00
Benjamin Kramer
f55d26e788 Implement mulo x, 2 -> addo x, x in DAGCombiner. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 18:31:55 +00:00
Cameron Zwarich
5a4b3d8c8f Fix PR9955 by only attaching load memory operands to load instructions and 
similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 23:44:34 +00:00
Stuart Hastings
3dfc4b1222 Update some currently-disabled code, preparing for eventual use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131663 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 18:48:20 +00:00
Duncan Sands
d6dde76090 Revert commit 131534 since it seems to have broken several buildbots. 
Original log entry:
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131536 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 14:57:56 +00:00
Nadav Rotem
fe3f5d7538 Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' 
code in one place.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 12:26:38 +00:00
Eli Friedman
9c4dae6b0b Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 23:02:10 +00:00
Dan Gohman
1b32896bd2 Misc. code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 22:22:52 +00:00
Dan Gohman
71dc7c9d89 Misc. code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 22:20:36 +00:00
Dan Gohman
975716af1b Delete unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 22:19:54 +00:00
Dan Gohman
b3dbd4a0b6 Trim #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 22:14:50 +00:00
Dan Gohman
f316eb7074 Fix whitespace and 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131428 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 22:09:53 +00:00
Jim Grosbach
62427ae8d3 Track how many insns fast-isel successfully selects as well as how many it 
misses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:51:07 +00:00
Devang Patel
227dfdb3c4 Preserve debug info for unused zero extended boolean argument. 
Radar 9422775.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:24:05 +00:00
Eli Friedman
482feb33b2 Make fast-isel work correctly s/uadd.with.overflow intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:06:17 +00:00
Eli Friedman
a4c920db7a Fix silly typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 20:34:53 +00:00
Eli Friedman
2586b8f936 Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131417 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 20:27:46 +00:00