This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22367 91177308-0d34-0410-b5e6-96231b3b80d8
MVTSDNode class. This class is used to provide an operand to operators
that require an extra type. We start by converting FP_ROUND_INREG and
SIGN_EXTEND_INREG over to using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22364 91177308-0d34-0410-b5e6-96231b3b80d8
For now, the elf writer is only capable of emitting an empty elf file, with
a section table and a section table string table. This will be enhanced
in the future :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22290 91177308-0d34-0410-b5e6-96231b3b80d8
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21676 91177308-0d34-0410-b5e6-96231b3b80d8
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21599 91177308-0d34-0410-b5e6-96231b3b80d8
when there are immediates, let's not worry about the memory overhead of
this :)
* add addU64Imm(uint64_t val) to machineinstrbuilder
(seriously: this seems required to support 64-bit immediates cleanly. if it
_really_ gets on your nerves, feel free to pull it out ;) )
coming up next week: "all your floating point constants are belong to us"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21208 91177308-0d34-0410-b5e6-96231b3b80d8
(which may or be function pointers) in the asmprinter. For the moment,
this changes nothing, except the IA64 backend which can use this to write:
data8.ua @fptr(blah__blah__mangled_function_name)
(by setting FunctionAddrPrefix/Suffix to "@fptr(" / ")")
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21024 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20988 91177308-0d34-0410-b5e6-96231b3b80d8
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
