6 Commits

Author	SHA1	Message	Date
Eli Friedman	7105259ce8	Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8	2011-07-16 02:41:28 +00:00
Sean Callanan	9a9d8b9732	Basic sanity checks to ensure that 2- and 3-byte ... VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8	2011-03-15 01:32:46 +00:00
Sean Callanan	8fbc00b5ba	Fixed a bug in the enhanced disassembler that caused ... it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8	2011-02-23 03:31:28 +00:00
Sean Callanan	ec243ae2b8	Added a testcase for the enhanced disassembly bug ... fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8	2011-02-22 02:19:18 +00:00
Rafael Espindola	2f867a63da	Correctly disassemble truncated asm. ... Patch by Richard Simth. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8	2011-01-06 16:48:42 +00:00
Dale Johannesen	2ae2302abc	Segregate tests by target. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119050 91177308-0d34-0410-b5e6-96231b3b80d8	2010-11-14 18:14:32 +00:00