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Author SHA1 Message Date
Rafael Espindola
5e6d548065 Move test to the X86 directory, note the PR number and only run MC once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 17:23:09 +00:00
Owen Anderson
fb6ab2b30e More not-crashing NEON disassembly updates for the vld refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 17:17:32 +00:00
NAKAMURA Takumi
4b2e07aa58 docs/*.html: Fix markups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 13:04:26 +00:00
NAKAMURA Takumi
5c6e4df713 docs/*.html: Appease W3C Checker to add "charset=utf-8". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 11:21:59 +00:00
Craig Topper
782c8fbd6e Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 07:16:37 +00:00
Craig Topper
593c1d9761 Test case for X86 FS/GS Base intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 02:15:47 +00:00
Craig Topper
6b1c5fc02a Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 02:15:10 +00:00
Nick Lewycky
1c929be810 Close <div> that was indenting the rest of the page. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 01:32:21 +00:00
Nick Lewycky
4e478fed1b Switch new .file directive emission off by default, change llc's flag for it to 
-enable-dwarf-directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 01:06:02 +00:00
Craig Topper
e7b05504fa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 19:57:21 +00:00
Duncan Sands
6dc9e2bf74 Reapply commit 143214 with a fix: m_ICmp doesn't match conditions 
with the given predicate, it matches any condition and returns the
predicate - d'oh!  Original commit message:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 19:56:36 +00:00
Craig Topper
26ec44f7cf Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 18:33:35 +00:00
Peter Collingbourne
8895316d04 Teach ModuleLinker::getLinkageResult about materialisable functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 17:46:34 +00:00
Benjamin Kramer
dade3c1448 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 17:31:21 +00:00
Craig Topper
6762427e8e Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 17:22:45 +00:00
Nadav Rotem
fb0dfbbff7 Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 13:24:22 +00:00
Benjamin Kramer
50bf86ea8a Silence compiler warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 08:39:55 +00:00
Nadav Rotem
5157588840 Stabilize the test by specifying an exact cpu target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 08:07:50 +00:00
Roman Divacky
223764c85b Update on PPC32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 07:49:04 +00:00
Bill Wendling
ac6d7e4911 Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143302 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 23:49:52 +00:00
NAKAMURA Takumi
7541867dbf CREDITS.TXT: Add a line. (test commit) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 23:42:14 +00:00
Nadav Rotem
b00418af67 Add a new DAGCombine optimization for BUILD_VECTOR. 
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 21:23:04 +00:00
Benjamin Kramer
f86545ecfd Force SSE for this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 19:43:44 +00:00
Benjamin Kramer
95c885d65a PPC: Disable moves for all CR subregisters. 
Should fix assertion failures on ppc buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 19:43:38 +00:00
Benjamin Kramer
59e43bde28 SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable. 
Fixes PR11264.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 19:43:31 +00:00
llvm
987d976efc Test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 14:16:39 +00:00
Bill Wendling
ae8538e3d5 Revise ThreadSanitizer mention so that it lists the correct frontends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 01:11:15 +00:00
Bill Wendling
63507d17d1 Add Cling to the External Projects list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 01:10:01 +00:00
Eli Friedman
09c3253d30 Revert r143214; it's breaking a bunch of stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143265 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 00:56:07 +00:00
Dan Gohman
6f3ddef7c5 Revert r143206, as there are still some failing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 00:41:52 +00:00
NAKAMURA Takumi
29ceb7c104 test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 23:11:03 +00:00
Jim Grosbach
e70ec84637 ARM mode 'mov' to 'mvn' assembler alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:50:54 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Jim Grosbach
48c1f84b10 Allow InstAlias's to use immediate matcher patterns that xform the value. 
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:32:53 +00:00
Owen Anderson
017f87cf68 Fix illegal disassembly testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143231 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 21:45:09 +00:00
Jim Grosbach
087f050bf9 Clarify example snippets a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 20:52:20 +00:00
Owen Anderson
b3727fe3ec Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 20:43:24 +00:00
Akira Hatanaka
feaa4c316f Make changes necessary in LowerFormalArguments to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
e42f33bd15 Make changes necessary in LowerCall to support Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:49:00 +00:00
Duncan Sands
012f8547f7 The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false. 
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 19:01:20 +00:00
Akira Hatanaka
2ec69faf26 Add variable IsO32 to MipsTargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:47:24 +00:00
Duncan Sands
4604fc7791 A shift of a power of two is a power of two or zero. 
For completeness - not spotted in the wild.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:30:05 +00:00
Duncan Sands
c65c747bc4 Fold icmp ugt (udiv X, Y), X to false. Spotted by my super-optimizer 
in 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:17:44 +00:00
Owen Anderson
cb9fed6655 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 18:02:13 +00:00
Dan Gohman
bf923b815d Reapply r143177 and r143179 (reverting r143188), with scheduler 
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:55:38 +00:00
Owen Anderson
82418ff4d1 Revert r143202. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:38:30 +00:00
Owen Anderson
7ccee5610a Specify fixed bits on CPS instructions to enable roundtripping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 17:29:39 +00:00
Jim Grosbach
5d0492cfc4 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:57:07 +00:00
Jim Grosbach
be5d6bcfc6 Allow register classes to match a containing class in InstAliases. 
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:43:40 +00:00
NAKAMURA Takumi
398daae4cc test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction. 
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 14:12:30 +00:00