Commit Graph

82 Commits

Author SHA1 Message Date
Dan Gohman
e4c67cdab4 Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-31 02:11:25 +00:00
Dan Gohman
ee4fa1977d Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03 00:02:49 +00:00
Chris Lattner
fe71893183 rename CodegenDAGPatterns -> CodeGenDAGPatterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45641 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06 01:10:31 +00:00
Chris Lattner
200c57e8ea now that computing CodegenDAGPatterns doesn't implicitly print stuff
out, DAGISelEmitter can compute it in its ctor, which simplifies some code.

Now we can use CodegenDAGPatterns in other parts of tblgen that want access
to dag pattern info, woo!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45636 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:58:54 +00:00
Chris Lattner
443e3f9dd6 move Node Transformation printing from CodeGenDAGPatterns -> DAGISelEmitter.
The only difference in output is that we now print them in alphabetical 
order instead of reverse alphabetical order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45635 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:54:53 +00:00
Chris Lattner
dc32f9802a move predicate printing code from CodeGenDAGPatterns -> DAGISelEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:43:57 +00:00
Chris Lattner
60d8139d1b fix a fixme by improving const correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45633 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:30:17 +00:00
Chris Lattner
6cefb77a70 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:25:12 +00:00
Chris Lattner
3060910e29 remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:37:13 +00:00
Evan Cheng
85dbe1a1d2 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41897 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-12 23:30:14 +00:00
Evan Cheng
a955939ca2 Refactor code to add initial support for OptionalDefOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37933 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:05:26 +00:00
Chris Lattner
efe9f4a3b6 Parse PredicateOperand's. When an instruction takes one, have the generated
isel fill in the instruction operands with the 'execute always' value
automatically.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31448 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-04 05:12:02 +00:00
Evan Cheng
94b3040fef Added properties such as SDNPHasChain to ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30890 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 21:02:01 +00:00
Evan Cheng
f549319b4a A bit more clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-26 01:02:19 +00:00
Evan Cheng
676d731c61 - Clean up tablegen dag isel generator code.
- Clean up the code generated by tablegen:
  * AddToISelQueue now takes one argument.
  * ComplexPattern matching condition can now be shared.
  * Eliminate passing unnecessary arguments to emit routines.
  * Eliminate some unneeded SDOperand declarations in select routines.
  * Other minor clean ups.
- This reduces foot print slightly: X86ISelDAGToDAG.o is reduced from 971k
  to 823k.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29892 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-26 00:59:04 +00:00
Evan Cheng
9bdca0302a Making TableGen'd instruction selection code non-recursive. This fixes PR805.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29548 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-07 22:17:58 +00:00
Evan Cheng
f872940dfc Parameterize target node ValueType to allow more sharing of emit functions.
Also reduce the number of arguments passed to emit functions and removed a
hack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-16 06:12:52 +00:00
Evan Cheng
fceb57a917 Reduce instruction selection code size and stack frame size by factoring
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29158 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-15 08:45:20 +00:00
Evan Cheng
2618d07765 Remove PointerType from target definition. Use abstract type MVT::iPTR to
represent pointer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28363 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 20:37:59 +00:00
Evan Cheng
c81d2a041d Rename AddedCost to AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27841 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 20:36:09 +00:00
Evan Cheng
5941320c0d Allow "let AddedCost = n in" to increase pattern complexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27834 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-19 18:07:24 +00:00
Chris Lattner
5a1df389a6 Change approach so that we get codegen for free for intrinsics. With this,
intrinsics that don't take pointer arguments now work.  For example, we can
compile this:

int test3( __m128d *A) {
  return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
  return _mm_movemask_ps(*A);
}

to this:

_test3:
        movl 4(%esp), %eax
        movapd (%eax), %xmm0
        movmskpd %xmm0, %eax
        ret
_test4:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        movmskps %xmm0, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27090 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 23:10:39 +00:00
Chris Lattner
550525e3cf Parse intrinsics correctly and perform type propagation. This doesn't currently
emit the code to select intrinsics, but that is next :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27082 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:48:51 +00:00
Evan Cheng
420132e1eb Copy matching pattern's output type info to instruction result pattern.
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26892 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 06:04:09 +00:00
Chris Lattner
697f88456c Add a new SDTCisIntVectorOfSameSize type constraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26890 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 05:39:48 +00:00
Evan Cheng
d7805a741d Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26084 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-09 07:16:09 +00:00
Evan Cheng
21ad392ee6 Hoist all SDOperand declarations within a Select_{opcode}() to the top level
to reduce stack memory usage. This is intended to work around the gcc bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26026 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-07 00:37:41 +00:00
Evan Cheng
e41bf82107 Allow more loads to be folded which were previously prevented from happening
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25995 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-05 06:43:12 +00:00
Chris Lattner
8bc7472a0c Factor matching code that is common between patterns. This works around
GCC not jump-threading across this common code, and produces far nicer
output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25762 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 04:25:26 +00:00
Chris Lattner
355408bcb7 move some code around, no change in the generated code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25758 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 02:43:35 +00:00
Jeff Cohen
9b0ffca478 Teach tablegen to generate code that is VC++ warning-free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25709 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:22:28 +00:00
Chris Lattner
09fb7d4dad fix a broken comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25411 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 21:31:18 +00:00
Evan Cheng
51fecc80f7 * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 18:27:06 +00:00
Nate Begeman
b73628b5ab Add support for generating v4i32 altivec code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-30 00:12:56 +00:00
Evan Cheng
7b05bd5814 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
support which is fragile.
* Fixed a number of bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 22:11:47 +00:00
Evan Cheng
9793888be8 * Added support for FLAG - a special nameless flag register. Can be used as
either an operand or a result.
* Fixed some more flag / chain bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24933 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22 02:24:50 +00:00
Evan Cheng
bcecf33dc2 Support for read / write from explicit registers with FlagVT type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:19:28 +00:00
Evan Cheng
58e84a69f5 Added support to specify predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24715 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:02:59 +00:00
Chris Lattner
5b21be76e1 Add a new SDTCisPtrTy constraint, which indicates that an operand must have
the same type as the pointer type for a target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24649 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 22:57:42 +00:00
Evan Cheng
b915f3110d * Do not allow nodes which produce chain results (e.g. loads) to be folded if
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
  operand of a chain use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24647 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 22:45:35 +00:00
Evan Cheng
cbc09c8eaa Prevent folding of instructions which produce chains that have more than 1 real use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24643 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 06:06:08 +00:00
Evan Cheng
c45146ace5 * Make sure complex pattern operands are selected first since their select
functions can return false and causing the instruction pattern match to fail.
* Code clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24642 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 00:48:42 +00:00
Evan Cheng
0fc7198890 Added support for ComplexPattern. These are patterns that require C++ pattern
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24634 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 02:00:36 +00:00
Evan Cheng
1c3d19eb15 * Commit the fix (by Chris) for a tblgen type inferencing bug.
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:18:16 +00:00
Evan Cheng
66a48bbc35 Teach tblgen to accept register source operands in patterns, e.g.
def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24557 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:18:45 +00:00
Nate Begeman
ddb395463c Stop checking the ValueType of the CodeGenInstruction. Instead, use the
ValueType from the RegisterClass or Operands.  This step is necessary to
allow RegisterClasses to have multiple ValueTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24555 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:06:14 +00:00
Chris Lattner
0614b628cf Add support for immediates directly in the pattern, this allows itanium to
define:

def : Pat<(i1 1), (CMPEQ r0, r0)>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24149 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 06:49:14 +00:00
Chris Lattner
edbd8711de Make tblgen emit:
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23854 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 01:19:59 +00:00
Chris Lattner
2ac8510d68 Fix some checking that was causing duraid to get a perplexing assertion
instead of a happy error message


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23816 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 04:12:14 +00:00
Chris Lattner
5024d93c8b Make the generated code significantly more memory efficient, by using
SelectNodeTo instead of getTargetNode when possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23758 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-16 01:41:58 +00:00