The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183802 91177308-0d34-0410-b5e6-96231b3b80d8
Most clients have already been moved from Path V1 to V2. The ones using V1
now include PathV1.h explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183801 91177308-0d34-0410-b5e6-96231b3b80d8
Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it.
This patch fixes both issues.
This patch fixes both, and the test should remain the same:
test/CodeGen/ARM/fast-isel-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183794 91177308-0d34-0410-b5e6-96231b3b80d8
For ARM on linux we use /proc/cpuinfo to detect the host CPU's features.
Linux derives these values without ever looking at the vendor of the
specific CPU implementation. Hence, it adds little value, if we parse
the output of /proc/cpuinfo only for certain vendors.
This patch enables us to derive the correct feature flags e.g. for Qualcomm
CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183790 91177308-0d34-0410-b5e6-96231b3b80d8
COFF header is always present both in executable and in object file. PE header
is present only in executable. So the natural way to handle PE/COFF file is
treating COFF is mandatory header and PE is optional. Current data structre
does not allow it, because PE header includes COFF header. Removing COFF
header will simplify the code to handle PE/COFF files.
Reviewers: Bigcheese
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D952
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Instead of a custom implementation of replaceAllUsesWith, we just call
replaceAllUsesWith and recreate llvm.used and llvm.compiler-used.
This change is particularity interesting because it makes llvm see
through what clang is doing with static used functions in extern "C"
contexts. With this change, running clang -O2 in
extern "C" {
__attribute__((used)) static void foo() {}
}
produces
@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to
i8*)], section "llvm.metadata"
define internal void @foo() #0 {
entry:
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183756 91177308-0d34-0410-b5e6-96231b3b80d8
It will be tested in the next commit which moves another user to identify_magic.
Original message:
Fix an out of bounds array access.
We were looking at Magic[5] without checking Length. Since this path would not
return unless Length >= 18 anyway, just move the >= 18 check up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183753 91177308-0d34-0410-b5e6-96231b3b80d8
This enables the compiler to see the enum and produce warnings about a switch
not being fully covered. Fix one of these warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183749 91177308-0d34-0410-b5e6-96231b3b80d8
The effect of llvm.used is to introduce an invisible reference, so this seems
a reasonable restriction. It will be used to provide an easy ordering of
the entries in llvm.used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183743 91177308-0d34-0410-b5e6-96231b3b80d8
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
- Don't use assert(0), or tests may pass or fail according to assertions.
- For now, The tests are marked as XFAIL for win32 hosts.
FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
Currently, only emitting the ELF header is supported (no sections or
segments).
The ELFYAML code organization is broadly similar to the COFFYAML code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183711 91177308-0d34-0410-b5e6-96231b3b80d8
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.
rdar://14024354
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