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5 Commits

Author SHA1 Message Date
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
NAKAMURA Takumi
69b5df8bf6 llvm/test/CodeGen/X86/zext-fold.ll: Relax an expression in stack offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147928 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-11 07:34:22 +00:00
Nick Lewycky
d61f84ee65 There's no need to be so picky about the particular register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 21:00:00 +00:00
Nick Lewycky
3cae396e03 Commit the right set of tests for r133124. Sorry 'bout that! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 01:35:45 +00:00
Nick Lewycky
c06b5bf340 Add a DAGCombine for (ext (binop (load x), cst)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 01:15:49 +00:00