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Author SHA1 Message Date
Chris Lattner
69a09e5677 Make testcase more interesting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4820 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 23:30:08 +00:00
Chris Lattner
1d53ce4067 Handle cmp Reg, 0 correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4819 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 23:30:00 +00:00
Chris Lattner
7ef33a9076 Printing support for more stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4818 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 22:49:46 +00:00
Chris Lattner
3a9a693987 Don't add implicit operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4817 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 22:49:20 +00:00
Chris Lattner
128a7a96f0 Fix off by one bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4816 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 22:48:15 +00:00
Chris Lattner
15207f45db Add fixme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4815 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 22:48:01 +00:00
Chris Lattner
47b4a9b2e0 Minor code cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4814 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 21:04:50 +00:00
Chris Lattner
1804233ca5 Implement printing of store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4813 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 21:03:39 +00:00
Chris Lattner
3d3067bf6b The big change here is to handle printing/emission of X86II::MRMSrcMem 
instructions.  Right now the only users are load instructions, and Misha's
spill code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4812 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 20:44:15 +00:00
Chris Lattner
92845e37f5 Remove implicit information from instruction selector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4811 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 18:54:29 +00:00
Chris Lattner
457adb55f9 Add printing information for MUL and DIV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4810 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 18:54:14 +00:00
Chris Lattner
94e8ee2282 Fix a bug that prevented compilation of multiple functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4809 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:26:58 +00:00
Chris Lattner
78c1d9037b Move test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4808 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:20:32 +00:00
Chris Lattner
9932bcddfc Shuffle testcases around 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4807 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:20:12 +00:00
Chris Lattner
2b905fdb81 New testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4806 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:18:37 +00:00
Chris Lattner
d3e0faca06 Remove opcode information for instructions that are completely defined now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4805 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:12:55 +00:00
Chris Lattner
644e3261d1 Add printing support for sahf & setcc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4804 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:10:57 +00:00
Chris Lattner
675dd2cc47 Add printing support for /0 /1 type instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4803 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:09:01 +00:00
Chris Lattner
85b39f229f Add support for /0 /1, etc type instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4802 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:08:49 +00:00
Chris Lattner
627079d42a User defined operators are not supposed to live beyond the lifetime of the 
pass.  Detect and flag them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4801 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 16:54:22 +00:00
Chris Lattner
4b4e9dd937 Rename the SetCC X86 instructions to reflect the fact that they are the 
register versions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4800 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 16:19:42 +00:00
Chris Lattner
05093a51b4 Simplify setcc code a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4799 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 15:52:38 +00:00
Chris Lattner
77875d88d0 Support Registers of the form (B8+ rd) for example 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4798 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 02:00:20 +00:00
Chris Lattner
97ad9e1fea Dont' set flags 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4797 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:59:50 +00:00
Chris Lattner
233ad71051 Implement printing more, implement opcode output more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4796 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:33:44 +00:00
Chris Lattner
0dc20dda5b Huge diff do to reindeinting comments. 
Basically just adds OpSize flags for instructions that need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4795 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:33:28 +00:00
Chris Lattner
11e53e3c38 Add new prefix flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4794 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:32:55 +00:00
Chris Lattner
644e1abae4 Print another class of instructions correctly, giving us: xorl EDX, EDX 
for example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4793 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 00:30:01 +00:00
Misha Brukman
7c58925050 Booleans are types too. And they get stored in bytes. And InstructionSelection 
doesn't assert fail. And everyone's happy. Yay!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4792 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 00:25:56 +00:00
Chris Lattner
d9624b04a1 Checkin testcases for bugpoint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4791 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 22:30:02 +00:00
Chris Lattner
21049cf266 Build bugpoint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4790 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 22:28:18 +00:00
Chris Lattner
afade9294a Initial checkin of bugpoint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4789 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 22:28:10 +00:00
Chris Lattner
51cbcbf435 Initial checkin of Module cloning support stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4788 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 20:47:41 +00:00
Chris Lattner
d4fd397805 Cloning stuff doesn't modify the source module 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4787 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 20:22:58 +00:00
Chris Lattner
900c23ced0 X86 target builds fine now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4786 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 20:17:03 +00:00
Chris Lattner
da3c8a7674 Fix symbol table problem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4785 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 19:32:43 +00:00
Misha Brukman
b83b28697c Add definitions for function headers from MRegisterInfo.h: 
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4784 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:59:43 +00:00
Misha Brukman
e1f0d8113a Check not only for MO_VirtualRegister, but MO_MachineRegister as well when 
printing out assembly. After all, we want the real thing too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4783 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:56:41 +00:00
Misha Brukman
b7825bc725 Initialize the SSARegMap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4782 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:55:27 +00:00
Misha Brukman
282ec57c4c MRegisterInfo.h - Added prototypes for functions we need to map a register to 
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:54:53 +00:00
Chris Lattner
cfe487296c Don't build X86 target yet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4780 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:37:37 +00:00
Chris Lattner
6e6026b465 - Eliminated the deferred symbol table stuff in Module & Function, it really 
wasn't an optimization and it was causing lots of bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4779 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:36:02 +00:00
Chris Lattner
c09aab0a4d Fix minor bugs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4778 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:32:31 +00:00
Chris Lattner
2c08dcc276 Eliminate the concept of a deferred symbol table. The optimization really isn't, 
and it causes obscure bugs to show up in passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4777 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:07:48 +00:00
Misha Brukman
d2cc017f46 Add mapping in MachineFunction from SSA regs to Register Classes. Also, 
uncovered a bug where registers were not being put in a map if they were not
found...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4776 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:58:23 +00:00
Misha Brukman
90ed18c201 Sigh. Fixed some speling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4775 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:56:42 +00:00
Misha Brukman
1617e6c997 SSARegMap -- the mapping between SSARegisters and their RegisterClasses, which 
imply types of SSA Registers. This is on a per-function basis, so the
MachineFunction contains the SSARegMap, and has accessor functions to it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4774 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:53:10 +00:00
Misha Brukman
602b9ff595 Thanks to the R8, R16, and R32 macros, I can now deal with registers that 
belong to different register classes easier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4773 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:47:40 +00:00
Chris Lattner
03b4c2d22a Remove unneccesary #include 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4772 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-19 23:12:53 +00:00
Chris Lattner
5a8932f57f Implement the CloneFunction function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4771 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-19 23:12:22 +00:00