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32 Commits

Author SHA1 Message Date
Elena Demikhovsky
94d7ab7da4 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 10:03:57 +00:00
Micah Villmow
3e9b6db60f Add in new data types that are used by AMDIL/ANL among others. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 22:47:07 +00:00
Micah Villmow
b3fb028ebd Add support for v16i32/v16i64 into the code generator. This is required for backends that use i32/i64 vectors for the getSetCCResultType function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 21:22:00 +00:00
Pete Cooper
ddfda5cd16 Added MVT::v2f16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 23:14:13 +00:00
Dan Gohman
e3376ecd50 Add basic generic CodeGen support for half. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:02:33 +00:00
Owen Anderson
23b0766b47 Fix formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 16:52:24 +00:00
Owen Anderson
77b4b13c2a Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 23:35:18 +00:00
Gabor Greif
0ccf6f14c8 fix comments; patch by Edmund Grimley-Evans\! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 17:52:00 +00:00
Dale Johannesen
d6934e4cee x86mmx is 64 bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 17:51:47 +00:00
Bill Wendling
d8dd5757e0 Add an MVT::x86mmx type. It will take the place of all current MMX vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:03:56 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 23:55:47 +00:00
Dan Gohman
e3040e4ae5 Move Flag and isVoid after the vector types, since bit arithmetic with 
those enum values is less common.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 23:36:03 +00:00
Bob Wilson
61fc4cf7aa Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsic 
arguments that are vectors of any size and element type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78631 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 01:14:02 +00:00
Duncan Sands
a4b0486684 Remove the v3i32 and v3f32 value types: they are not 
native for any supported targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:28:52 +00:00
Bob Wilson
86c13cd733 Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75612 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 06:09:50 +00:00
Bob Wilson
ab5a5a6a76 Revert 75308. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:16:03 +00:00
Bob Wilson
28eff96ee6 Add new vector types for 192-bit, 348-bit and 512-bit sizes. 
These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4
separate vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75308 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 23:05:09 +00:00
Devang Patel
bee9e35ba2 Add new ValueType for metadata. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74882 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 23:44:32 +00:00
David Greene
9b9838dbd4 Add more vector ValueTypes for AVX and other extended vector instruction 
sets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 16:47:10 +00:00
Mon P Wang
87c8a8f304 Added support for vector widening. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-18 20:03:17 +00:00
Mon P Wang
e3b3a7241c Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 04:36:53 +00:00
Chris Lattner
234d529e58 remove attribution from a variety of miscellaneous files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45425 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 22:59:10 +00:00
Dan Gohman
0fee3ff93e Add MVT::fAny for overloading intrinsics on floating-point types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-16 21:57:19 +00:00
Chandler Carruth
6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-04 01:51:18 +00:00
Dale Johannesen
e713d9340a long double patch 3 of N. Add to MVT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40793 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 20:51:37 +00:00
Christopher Lamb
9e1e81ccbe Fix comments for new types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40507 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 01:48:57 +00:00
Christopher Lamb
1fcc4b2ba8 Add support for 3 element 32-bit vector ValueTypes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 01:46:52 +00:00
Dan Gohman
798cb2ab82 Renumber the SimpleValueType values to fill in the hole left by 
removing MVT::Vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37730 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 14:28:59 +00:00
Reid Spencer
86a5a368f8 For PR1297: 
Add an "iAny" ValueType as a place holder for an integer type of any
bit width. This is used for intrinsics overloading on integer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35538 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:17:45 +00:00
Chris Lattner
0d3988f408 add a valuetype for v1i64, which is needed by mmx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35298 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 17:36:26 +00:00
Chris Lattner
e1562c82ca add a new iPTR ValueType for tblgen use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27187 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 22:48:00 +00:00
Chris Lattner
c1323faa74 Split this out of Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26488 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 01:54:11 +00:00