4 Commits

Author	SHA1	Message	Date
Tim Northover	936285440b	AArch64/ARM64: port more AArch64 tests to ARM64. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206592 91177308-0d34-0410-b5e6-96231b3b80d8	2014-04-18 13:16:55 +00:00
Tim Northover	069bcd7b38	AArch64: add newline to end of test files. ... Should be no other change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206174 91177308-0d34-0410-b5e6-96231b3b80d8	2014-04-14 13:18:40 +00:00
Hao Liu	a339740cb8	[AArch64]Add missing pair intrinsics such as: ... int32_t vminv_s32(int32x2_t a) which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196749 91177308-0d34-0410-b5e6-96231b3b80d8	2013-12-09 03:51:42 +00:00
Tim Northover	87773c318f	AArch64: add initial NEON support ... Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8	2013-08-01 09:20:35 +00:00