Commit Graph

104856 Commits

Author SHA1 Message Date
David Blaikie
0c2029af03 test/DebugInfo/X86/dbg-value-isel.s: correct lexical block descriptor to match schema
This silently broke a long time ago when I unified some aspects of the
debug info schema. I'm just cleaning these up if/when they become a
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210939 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 21:52:28 +00:00
Zachary Turner
89e90b25e3 Make the error-handling functions thread-safe.
Prior to this change, error handling functions must be installed
and removed only inside of an llvm_[start/stop]_multithreading
pair.  This change allows error handling functions to be installed
any time, and from any thread.

Reviewed by: chandlerc

Differential Revision: http://reviews.llvm.org/D4140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210937 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 21:20:44 +00:00
Alexey Samsonov
6140939365 Remove top-level Clang -fsanitize= flags for optional ASan features.
Init-order and use-after-return modes can currently be enabled
by runtime flags. use-after-scope mode is not really working at the
moment.

The only problem I see is that users won't be able to disable extra
instrumentation for init-order and use-after-scope by a top-level Clang flag.
But this instrumentation was implicitly enabled for quite a while and
we didn't hear from users hurt by it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210924 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 17:53:44 +00:00
Tim Northover
eee7a7a836 X86: lower ATOMIC_CMP_SWAP_WITH_SUCCESS directly
Lowering this new node allows us to fold the almost universal
comparison for success before it's even formed. Instead we can create
a copy from EFLAGS and an X86ISD::SETCC operation since all "cmpxchg"
instructions set the zero-flag to the correct value.

rdar://problem/13201607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210923 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 17:29:39 +00:00
Matt Arsenault
f317d86f8f R600: Cleanup some old AMDIL stuff.
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 17:20:53 +00:00
Rafael Espindola
d8b23109b2 Finishing touch for the std::error_code transition.
While std::error_code itself seems to work OK in all platforms, there
are few annoying differences with regards to the std::errc enumeration.

This patch adds a simple llvm enumeration, which will hopefully avoid build
breakages in other platforms and surprises as we get more uses of
std::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 17:20:48 +00:00
Tim Northover
33fe993f2e Atomics: make use of the "cmpxchg weak" instruction.
This also simplifies the IR we create slightly: instead of working out
where success & failure should go manually, it turns out we can just
always jump to a success/failure block created for the purpose. Later
phases will sort out the mess without much difficulty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210917 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 16:45:52 +00:00
Tim Northover
6b3ed2b821 Atomics: switch direction of cmpxchg comparison
This has two benefits: it makes the result more suitable for direct
insertaion into the struct to emulate the new cmpxchg, and it means
the name we give the instruction matches its actual effect better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210916 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 16:45:36 +00:00
Tom Stellard
61bc72e9ae R600: Remove AMDIL instruction and register definitions
Most of these are no longer used any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 16:38:59 +00:00
Tobias Grosser
df46288714 opt: Initialize asm printers
Without initializing the assembly printers a shared library build of opt is
linked with these libraries whereas for a static build these libraries are dead
code eliminated. This is unfortunate for plugins in case they want to use them,
as they neither can rely on opt to provide this functionality nor can they link
the printers in themselves as this breaks with a shared object build of opt.

This patch calls InitializeAllAsmPrinters() from opt, which increases the static
binary size from 50MB -> 52MB on my system (all backends compiled) and causes no
measurable increase in the time needed to run 'make check'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210914 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 16:12:08 +00:00
Rafael Espindola
cc0d35a2e8 Remove unused and odd code.
This code was never being used and any use of it would look fairly strange.
For example, it would try to map a object_error::parse_failed to
std::errc::invalid_argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210912 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 15:36:17 +00:00
Rafael Espindola
520ae5c765 Remove broken include.
Looks like I got some git merge wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210911 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 15:21:50 +00:00
Rafael Espindola
087c5bc9f1 Fix KillTheDoctor after r210725.
We don't map these windows errors to generic ones since errc::timed_out is
not defined on mingw. Just use the raw windows error value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210910 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 15:01:11 +00:00
Tim Northover
e1a9d504a3 SCCP: update for cmpxchg returning { iN, i1 } now.
I accidentally missed this one since its use looked OK locally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210909 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:54:09 +00:00
Zoran Jovanovic
636ae2b660 [mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:26:47 +00:00
Tim Northover
6eaf840a3d Docs: remove extra {} around result types.
It makes the types look like they're single-element structures. And
when we have instructions that *do* result in a struct, that can get
confusing rather quickly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210905 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:23 +00:00
Tim Northover
ab47c159b0 Docs: fix grammar error in description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:16 +00:00
Tim Northover
8f2a85e099 IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.

As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.

At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.

By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.

Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.

Summary for out of tree users:
------------------------------

+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
Cameron McInally
1d5e37946d Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:20:01 +00:00
Daniel Sanders
7cfd0ffb3b [mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:15:59 +00:00
Daniel Sanders
ef8e567137 [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6
Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4115

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:08:38 +00:00
Daniel Sanders
21ed78f564 [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction
Summary:
b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias
for 'bgezal $zero, $offset') still remains with the same encoding it had
prior to MIPS32r6/MIPS64r6.

Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the
MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo.

No changes were required to the CodeGen test that looks for BAL
(test/CodeGen/Mips/longbranch.ll) since the new instruction has the same
syntax.

Depends on D4113

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:02:52 +00:00
Daniel Sanders
21c016f699 [mips][mips64r6] daddi is not available on MIPS64r6
Summary:
It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4113

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 12:49:06 +00:00
NAKAMURA Takumi
94afbc661f [Win32] Let utils/not aware of abort(), aka llvm_unreachable(), in msvcrt.
It has exit code as 3. abort(), aka unreachable, may be handled as crash.

FIXME: Could we move this into Win32/Program.inc?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210895 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 12:23:56 +00:00
NAKAMURA Takumi
c5865cb4fc llvm/test/CodeGen/X86/fast-isel-args-fail2.ll: Don't expect to fail with -Asserts. It might or might not crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 12:05:06 +00:00
Cameron McInally
a411d0e631 Add HasCDI predicate to AVX512 VPBROADCASTM*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210892 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 11:40:31 +00:00
Tim Northover
d5d864b553 CPP backend: set volatile property on atomic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 09:14:50 +00:00
Oliver Stannard
a19c2d4a6d ARM: Fix fastcc calling convention for Thumb1
When targetting Thumb1 on a processor which has a VFP unit (which
is not accessible from Thumb1), we were converting the fastcc calling
convention to AAPCS-VFP, which is not possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 08:33:03 +00:00
Matt Arsenault
efa4805b58 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 07:44:38 +00:00
Matt Arsenault
d344c6bcf9 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 04:00:30 +00:00
Rafael Espindola
250305156a Remove the last uses of 'using std::error_code'
This finishes the transition to std::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 03:20:08 +00:00
Rafael Espindola
1ad45020ec Remove 'using std::error_code' from tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 03:07:50 +00:00
Rafael Espindola
7532b4038f Fix build on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 02:36:09 +00:00
Rafael Espindola
4e2b922131 Remove 'using std::errro_code' from lib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210871 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 02:24:39 +00:00
Juergen Ributzka
e431884ed7 [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.
This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding
insertelement instructions are folded into the conversion instruction (if
possible).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210870 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 02:21:58 +00:00
Tom Stellard
6b0a08b15b R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:32:00 +00:00
Tom Stellard
ee0f3892f9 R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:31:56 +00:00
Rafael Espindola
a20bcb9969 Remove all uses of 'using std::error_code' from headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:25:41 +00:00
Tom Stellard
aa48b83e80 R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 01:02:57 +00:00
Juergen Ributzka
7f8d138f50 [FastISel][X86] - Add branch weights
Add branch weights to branch instructions, so that the following passes can
optimize based on it (i.e. basic block ordering).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 00:45:11 +00:00
Eric Christopher
f7a2d5e387 Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 00:20:39 +00:00
Eric Christopher
1ee246100e Move to a private function to initialize subtarget dependencies
so we can use initializer lists for the ARMSubtarget and then
use this to initialize a moved DataLayout on the subtarget from
the TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 00:20:35 +00:00
Alexey Samsonov
740a75968a [DWARF parser] Fix broken address ranges construction.
Previous algorithm for constructing [Address ranges]->[Compile Units]
mapping was wrong. It somewhat relied on the assumption that address ranges
for different compile units may not overlap. It is not so.
For example, two compile units may contain the definition of the same
linkonce_odr function. These definitions will be merged at link-time,
resulting in equivalent .debug_ranges entries for both these units

Instead of sorting and merging original address ranges (from .debug_ranges
and .debug_aranges), implement a different approach: save endpoints
of all ranges, and then use a sweep-line approach to construct
the desired mapping. If we find that certain address maps to
several compilation units, we just pick any of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 23:58:49 +00:00
Eric Christopher
9a81e28056 Have ARMSelectionDAGInfo take a DataLayout as it's argument as the
DAG has access to the subtarget and TargetSelectionDAGInfo only
needs a DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210859 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 23:39:49 +00:00
Juergen Ributzka
4eddf94a14 [FastISel][X86] Add MachineMemOperand to load/store instructions.
This commit adds MachineMemOperands to load and store instructions. This allows
the peephole optimizer to fold load instructions. Unfortunatelly the peephole
optimizer currently doesn't run at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 23:27:57 +00:00
Eric Christopher
cccc317ee0 Move the PPCSelectionDAGInfo off the TargetMachine and onto the
subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210854 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 23:02:32 +00:00
Eric Christopher
8c5dc520ef Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachine
since that's all it needs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210853 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 22:56:48 +00:00
Eric Christopher
a7159144c2 Move PPCTargetLowering off of the TargetMachine and onto the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210852 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 22:50:10 +00:00
Eric Christopher
cb7dc25df1 Remove an extraneous this-> to access the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210849 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 22:38:20 +00:00
Eric Christopher
f6b9efa7db Rename PPCSubTarget to Subtarget in PPCTargetLowering for consistency.
Also remove an extra local subtarget in the initialization functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 22:38:18 +00:00