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Commit Graph

3650 Commits

Author SHA1 Message Date
Michael Kuperstein
765aab84d6 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233068 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 12:56:59 +00:00
Michael Kuperstein
d3ab717935 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233055 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 09:17:25 +00:00
Benjamin Kramer
eef4a339b5 Another set of missing raw_ostream.h. Still no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232993 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:56 +00:00
Craig Topper
3220d112fa [Tablegen] Attempt to add support for patterns containing nodes with multiple results.
This is needed for AVX512 masked scatter/gather support.

The R600 change is necessary to remove a hack that was working around the lack of multiple results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-20 05:09:06 +00:00
Matthias Braun
5101c89f13 Do not track subregister liveness when it brings no benefits
Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multiple
disjunct parts. Avoid tracking subregister liveness in these cases as it
is not beneficial.

Differential Revision: http://reviews.llvm.org/D8429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-19 00:21:58 +00:00
Matthias Braun
8b41add6ca TableGen: Fix register class lane masks being too conservative.
When calculating the lanemask of a register class we have to include the
masks of subregisters supported by any of the class members, not just
the ones supported by all class members.

This fixes problems when coalescing towards a subclass with additional
subregisters available.

The attached testcase works fine as is, but does crash if you enable
subregister liveness on x86 without this change applied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232652 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 17:56:09 +00:00
Yaron Keren
703b185464 Remove many superfluous SmallString::str() calls.
Now that SmallString is a first-class citizen, most SmallString::str()
calls are not required. This patch removes a whole bunch of them, yet
there are lots more.

There are two use cases where str() is really needed:
1) To use one of StringRef member functions which is not available in
SmallString.
2) To convert to std::string, as StringRef implicitly converts while 
SmallString do not. We may wish to change this, but it may introduce
ambiguity.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232622 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 10:17:07 +00:00
Eric Christopher
c666f5df88 Use the variable names from the TargetInstrInfo source when we
reference them in the generated files. A few characters aren't huge
here and CFSetupOpcode is much more readable than S0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232132 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 01:26:39 +00:00
Eric Christopher
4223496f24 Add a return after the llvm namespace code for a little extra
readability in generated files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232131 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 01:10:08 +00:00
Eric Christopher
138fe781d2 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231951 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 18:34:58 +00:00
Yaron Keren
1132d0cc5b Teach raw_ostream to accept SmallString.
Saves adding .str() call to any raw_ostream << SmallString usage
and a small step towards making .str() consistent in the ADTs by
removing one of the SmallString::str() use cases, discussion at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html

I'll update the Phabricator patch http://reviews.llvm.org/D6372
for review of the Twine SmallString support, it's more complex
than this one.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231763 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 07:33:23 +00:00
Craig Topper
d4843f4c45 Improve and simplify EnforceSmallerThan for vector types.
Explicitly compare the size of the scalar types and the whole vector size rather than just comparing enum encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231746 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 03:25:07 +00:00
Craig Topper
541e68ea57 Remove extra indentation of entire function body. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231745 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 03:25:04 +00:00
Reid Kleckner
fe8490c22e TableGen: Use 'enum : uint64_t' for feature flags to fix -Wmicrosoft
clang-cl would warn that this value is not representable in 'int':
  enum { FeatureX = 1ULL << 31 };
All MS enums are 'ints' unless otherwise specified, so we have to use an
explicit type.  The AMDGPU target just hit 32 features, triggering this
warning.

Now that we have C++11 strong enum types, we can also eliminate the
'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 20:23:14 +00:00
Tom Stellard
98225d9c9c TableGen: Initialize ErrorInfo to ~0ULL in the MatchInstructionImpl
This is what all the targets check for and is consistent with the
initialized value of MissingFeatures, which is sometimes assinged
to ErrorInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231397 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 19:46:55 +00:00
Craig Topper
bc55462859 Revert "[TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns."
This is failing on several build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231358 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 07:17:52 +00:00
Craig Topper
256cb3b576 [TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns.
This should help with the AVX512 masked gather changes Elena is working on. This patch is derived from some of the changes Elena made to tablegen, but modified by me to support arbitrary number of results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231357 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 07:11:36 +00:00
Craig Topper
8ad519fd3c [TableGen] Add support constraining a vector type in a pattern to have a specific element type and for constraining a vector type to have the same number of elements as another vector type. This is useful for AVX512 mask operations so we relate the mask type to the type of the other arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231356 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-05 07:11:34 +00:00
David Blaikie
5109ec06a6 Add a FIXME for PR22796, broken ordering of ClassInfo in TableGen
As discussed (at length) in code review of r222935, with Duncan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231282 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 19:56:44 +00:00
Craig Topper
b660ece860 [Tablegen] Use correct result number variables with the pattern nodes they go with when handling SDTCisSameAs. No functional change as they are always both 0 unless you try to define a multi result type profile that uses SDTCisSame on one of the other results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231226 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-04 09:04:54 +00:00
David Blaikie
317ccafdbd Revert "Remove the explicit SDNodeIterator::operator= in favor of the implicit default"
Accidentally committed a few more of these cleanup changes than
intended. Still breaking these out & tidying them up.

This reverts commit r231135.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231136 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 21:18:16 +00:00
David Blaikie
b13215ec3b Remove the explicit SDNodeIterator::operator= in favor of the implicit default
There doesn't seem to be any need to assert that iterator assignment is
between iterators over the same node - if you want to reuse an iterator
variable to iterate another node, that's perfectly acceptable. Just
don't mix comparisons between iterators into disjoint sequences, as
usual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231135 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 21:17:08 +00:00
Nick Lewycky
ca99858baa Switch up whitespace with better whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231059 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 07:59:45 +00:00
Nick Lewycky
146db69645 Revert the non-cleanup part of r230769 because it introduced a non-determinism found only in the names of symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 07:57:45 +00:00
Benjamin Kramer
e1244e83b9 TblGen: Remove copy of SmallVector::operator==. NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230964 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-02 15:24:30 +00:00
Benjamin Kramer
d59c5f9a06 Add missing includes. make_unique proliferated everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230909 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 21:28:53 +00:00
Elena Demikhovsky
bf4d9a8aaf Reverted 230471 - gather scatter handling in table gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230892 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 08:23:41 +00:00
Elena Demikhovsky
975e9b99aa AVX-512: Added mask and rounding mode for scalar arithmetics
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-01 07:44:04 +00:00
Yaron Keren
fa22cce8d7 Silence variable set but not used warning in CodeGenRegisters.cpp, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230854 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-28 15:54:04 +00:00
Benjamin Kramer
31fbd9f7b0 Replace std::copy with a back inserter with vector append where feasible
All of the cases were just appending from random access iterators to a
vector. Using insert/append can grow the vector to the perfect size
directly and moves the growing out of the loop. No intended functionalty
change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-28 10:11:12 +00:00
Owen Anderson
ecf670391b Switch a std::map to a DenseMap in CodeGenRegisters.
The keys of the map are unique by pointer address, so there's no need
to use the llvm::less comparator. This allows us to use DenseMap
instead, which reduces tblgen time by 20% on my stress test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 17:57:01 +00:00
Reid Kleckner
138aa39eac Re-instate the pragma optimize hack for MSVC, but not clang-cl
Reverts commit r230686 with define modifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230692 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 21:34:11 +00:00
Reid Kleckner
cc3bcaea20 Remove stale pragma hack for an unsupported MSVC version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 21:08:27 +00:00
Eric Christopher
435571ada6 Fix a couple of depedent->dependent typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230584 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 00:00:33 +00:00
Elena Demikhovsky
4105fd49d4 AVX-512: Gather and Scatter patterns
Gather and scatter instructions additionally write to one of the source operands - mask register.
In this case Gather has 2 destination values - the loaded value and the mask.
Till now we did not support code gen pattern for gather - the instruction was generated from 
intrinsic only and machine node was hardcoded.
When we introduce the masked_gather node, we need to select instruction automatically,
in the standard way.
I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands.

(Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big
patch in many small patches)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230471 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-25 09:46:31 +00:00
Tim Northover
ca7e0787f0 CodeGen: convert CCState interface to using ArrayRefs
Everyone except R600 was manually passing the length of a static array
at each callsite, calculated in a variety of interesting ways. Far
easier to let ArrayRef handle that.

There should be no functional change, but out of tree targets may have
to tweak their calls as with these examples.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230118 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-21 02:11:17 +00:00
Michael Kuperstein
2b5910a767 Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-19 11:38:11 +00:00
Michael Kuperstein
23dd089d8f Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-19 09:01:04 +00:00
Aaron Ballman
4e521d9500 MSVC 2013 does not ICE on this code in the same fashion that MSVC 2012 did; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229422 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-16 19:33:36 +00:00
Aaron Ballman
66981fe208 Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229340 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-15 22:54:22 +00:00
Craig Topper
e2f7231e45 [X86] Add the remaining 11 possible exact ModRM formats. This makes their encodings linear which can then be used to simplify some other code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229279 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-15 04:16:44 +00:00
Craig Topper
f3455f13a2 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229078 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-13 07:42:25 +00:00
Benjamin Kramer
d913d9d2c3 MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line with countTrailingZeros
Update all callers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-12 15:35:40 +00:00
Elena Demikhovsky
8be39c81b0 Masked Gather and Scatter Intrinsics.
Gather and Scatter are new introduced intrinsics, comming after recently implemented masked load and store.
This is the first patch for Gather and Scatter intrinsics. It includes only the syntax, parsing and verification.

Gather and Scatter intrinsics allow to perform multiple memory accesses (read/write) in one vector instruction.
The intrinsics are not target specific and will have the following syntax:
Gather:
declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1> <mask>, <16 x i32> <passthru>)
declare <8 x float> @llvm.masked.gather.v8f32(<8 x float*><vector of ptrs>, i32 <alignment>, <8 x i1> <mask>, <8 x float><passthru>)

Scatter:
declare void @llvm.masked.scatter.v8i32(<8 x i32><vector value to be stored> , <8 x i32*><vector of ptrs> , i32 <alignment>, <8 x i1> <mask>)
declare void @llvm.masked.scatter.v16i32(<16 x i32> <vector value to be stored> , <16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1><mask> )

Vector of ptrs - a set of source/destination addresses, to load/store the value. 
Mask - switches on/off vector lanes to prevent memory access for switched-off lanes
vector of ptrs, value and mask should have the same vector width.

These are code examples where gather / scatter should be used and will allow function vectorization
;void foo1(int * restrict A, int * restrict B, int * restrict C) {
; for (int i=0; i<SIZE; i++) {
; A[i] = B[C[i]];
; }
;}

;void foo3(int * restrict A, int * restrict B) {
; for (int i=0; i<SIZE; i++) {
; A[B[i]] = i+5;
; }
;}

Tests will come in the following patches, with CodeGen and Vectorizer.

http://reviews.llvm.org/D7433



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-08 08:27:19 +00:00
David Blaikie
fb29a70867 STLExtras: Provide less/equal functors with templated function call operators, plus a deref'ing functor template utility
Similar to the C++14 void specializations of these templates, useful as
a stop-gap until LLVM switches to '14.

Example use-cases in tblgen because I saw some functors that looked like
they could be simplified/refactored.

Reviewers: dexonsmith

Differential Revision: http://reviews.llvm.org/D7324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227828 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-02 18:35:10 +00:00
Owen Anderson
41a9ae532e Replace another std::set in the core of CodeGenRegister, this time with sorted arrays.
The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-31 09:13:36 +00:00
Owen Anderson
35da384515 Change more of the guts of CodeGenRegister's RegUnit tracking to be based on bit vectors.
This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227678 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-31 07:49:41 +00:00
Owen Anderson
bc227b65c2 Change a very hot piece of code in TableGen's register unit computations to use bit vectors rather than arrays.
For target descriptions with very large and very dense register files, TableGen
can take an extremely long time to run.  This change makes a dent in that (~15%
in my measurements) by accelerating the single hottest operation with better data
structures.

I believe there's still a lot of room to make this even faster with more global
changes that require replacing some of the existing datastructures in this area
with bit vectors, but that's a more involved change and I wanted to get this
simpler improvement in first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227562 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 09:05:49 +00:00
Craig Topper
aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 10:09:56 +00:00
Eric Christopher
04bcc11905 Move DataLayout back to the TargetMachine from TargetSubtargetInfo
derived classes.

Since global data alignment, layout, and mangling is often based on the
DataLayout, move it to the TargetMachine. This ensures that global
data is going to be layed out and mangled consistently if the subtarget
changes on a per function basis. Prior to this all targets(*) have
had subtarget dependent code moved out and onto the TargetMachine.

*One target hasn't been migrated as part of this change: R600. The
R600 port has, as a subtarget feature, the size of pointers and
this affects global data layout. I've currently hacked in a FIXME
to enable progress, but the port needs to be updated to either pass
the 64-bitness to the TargetMachine, or fix the DataLayout to
avoid subtarget dependent features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-26 19:03:15 +00:00