Commit Graph

427 Commits

Author SHA1 Message Date
Matt Arsenault
3c698f35e0 R600: Try to convert BFE back to standard bit ops when possible.
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:12 +00:00
Matt Arsenault
e3ed404672 R600: Add dag combine for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:07 +00:00
Matt Arsenault
7e12b82625 R600: Implement ComputeNumSignBitsForTargetNode for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:03 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:15 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 03:20:30 +00:00
Matt Arsenault
bd124c85ef R600: Partially fix constant initializers for structs and vectors.
This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:42 +00:00
Matt Arsenault
713096fb68 R600: Add failing testcases for constant initializers.
Constant initializers involving illegal types hit an assertion.

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:38 +00:00
Tom Stellard
3bd63cd655 R600/SI: Promote f32 SELECT to i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:41 +00:00
Tom Stellard
c1de569ce8 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:54 +00:00
Tom Stellard
bfffad69b2 R600/SI: Use VALU instructions for i1 ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:50 +00:00
Jay Foad
6b543713a2 Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 21:14:37 +00:00
Matt Arsenault
dda22295e4 R600/SI: Try to fix BFE operands when moving to VALU
This was broken by r208479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 23:45:50 +00:00
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:49:57 +00:00
Matt Arsenault
621299806c Make SimplifyDemandedBits understand BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:14:48 +00:00
Vincent Lejeune
e283f74133 R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:39 +00:00
Vincent Lejeune
3378ca7d5c R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:33 +00:00
Tom Stellard
3f26d366a4 R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208432 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:22 +00:00
Tom Stellard
300094fd84 R600/SI: Fix SMRD pattern for offsets > 32 bits
We were dropping the high bits of 64-bit immediate offsets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208431 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:21 +00:00
Tom Stellard
561bb44525 R600: Expand i64 SELECT_CC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208430 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:19 +00:00
Tom Stellard
87b983680c R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:16 +00:00
Tom Stellard
4b84b524e5 R600: Expand i64 ISD:SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208005 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 21:47:15 +00:00
Tom Stellard
ab2fed6622 R600: Expand vector sin and cos.
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:47 +00:00
Tom Stellard
1d6859256c R600: Expand TruncStore i64 -> {i16,i8}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207844 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:46 +00:00
Matt Arsenault
2baa7c53c9 R600/SI: Fix verifier error with pseudo store instructions.
Use i32 instead of specifying SReg_32. When this is
the pseudo INDIRECT_BASE_ADDR, this would give a bogus
verifier error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207770 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 16:37:52 +00:00
Tom Stellard
bd24b33e57 R600/SI: Use VALU instructions for copying i1 values
We can't use SALU instructions for this since they ignore the EXEC mask
and are always executed.

This fixes several OpenCV tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:31:33 +00:00
Tom Stellard
1d8e31fc7a R600/SI: Teach moveToVALU how to handle some SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:31:29 +00:00
Tom Stellard
40e455d992 R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
SI_IF and SI_ELSE are terminators which also produce a value.  For
these instructions ISel always inserts a COPY to move their value
to another basic block.  This COPY ends up between SI_(IF|ELSE)
and the S_BRANCH* instruction at the end of the block.

This breaks MachineBasicBlock::getFirstTerminator() and also the
machine verifier which assumes that terminators are grouped together at
the end of blocks.

To solve this we coalesce the copy away right after ISel to make sure
there are no instructions in between terminators at the end of blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:53 +00:00
Tom Stellard
2a90e446c0 R600/SI: Only select SALU instructions in the entry or exit block
SALU instructions ignore control flow, so it is not always safe to use
them within branches.  This is a partial solution to this problem
until we can come up with something better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:48 +00:00
Tom Stellard
19a970b2da R600: optimize the UDIVREM 64 algorithm
This is a squash of several optimization commits:
 - calculate DIV_Lo and DIV_Hi separately
 - use BFE_U32 if we are operating on 32bit values
 - use precomputed constants instead of shifting in UDVIREM
 - skip the first 32 iterations of udivrem

v2: Check whether BFE is supported before using it

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:46 +00:00
Matt Arsenault
6cd6974e56 R600: Add a test that used to be broken that I forgot to add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207017 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 19:45:05 +00:00
Matt Arsenault
3682fdabef R600: Emit error instead of unreachable on function call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:42:00 +00:00
Matt Arsenault
3ddf868b04 R600: Make sign_extend_inreg legal.
Don't know why I didn't just do this in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:49:30 +00:00
Matt Arsenault
746734df1a R600/SI: Try to use scalar BFE.
Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 05:19:26 +00:00
Matt Arsenault
6834a55df3 R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206547 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 01:53:18 +00:00
Tom Stellard
cfe02c46dc R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 00:36:21 +00:00
Tom Stellard
93ea1378d2 R600/SI: Stop using i128 as the resource descriptor type
Having i128 as a legal type complicates the legalization phase.  v4i32
is already a legal type, so we will use that instead.

This fixes several piglit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:11 +00:00
Matt Arsenault
9e383d4b48 R600/SI: f64 frint is legal on CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 17:06:37 +00:00
Matt Arsenault
003de065a3 R600/SI: Fix zext from i1 to i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 02:03:08 +00:00
Matt Arsenault
9fde950b1b R600: Extend r600 sign_extend_inreg tests for EG
Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 01:41:34 +00:00
Matt Arsenault
bec5c611e1 R600/SI: Print more immediates in hex format
Print in decimal for inline immediates, and hex otherwise. Use hex
always for offsets in addressing offsets.

This approximately matches what the shader compiler does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:32:49 +00:00
Matt Arsenault
f8ea0352e0 R600/SI: Fix loads of i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:28:39 +00:00
Tom Stellard
e04360918b SelectionDAG: Use helper function to improve legalization of ISD::MUL
The TargetLowering::expandMUL() helper contains lowering code extracted
from the DAGTypeLegalizer and allows the SelectionDAGLegalizer to expand more
ISD::MUL patterns without having to use a library call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206037 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 16:12:01 +00:00
Matt Arsenault
d4786ed1de R600/SI: Match not instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 07:16:16 +00:00
Tom Stellard
1d8c7eb225 R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:45 +00:00
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:41 +00:00
Tom Stellard
a7469745de R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4

Fixes Arithm/Absdiff.Mat/3 OpenCV test

Patch by: Bruno Jiménez

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:29 +00:00
Tom Stellard
50c16fb65c R600/SI: Lower 64-bit immediates using REG_SEQUENCE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:27 +00:00
Tom Stellard
adb852ddf3 TargetLibraryInfo: Disable memcpy and memset on R600
There are no implementations of these for R600.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-02 19:53:29 +00:00