Elena Demikhovsky
e3e08acd09
AVX-512: optimized a shuffle pattern to VINSERTI64x4.
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Added intrinsics for VPERMT2PS/PD/D/Q instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 09:09:15 +00:00
Elena Demikhovsky
002683abc7
AVX-512: Added intrinsic for cvtph2ps.
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Added VPTESTNM instruction.
Added a pattern to vselect (lit tests will follow).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200823 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 07:05:03 +00:00
Elena Demikhovsky
e1a621d84f
AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,
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they give better sequences than VPERMI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199893 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 14:27:26 +00:00
Elena Demikhovsky
3bf51cf302
AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC.
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I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11 14:31:04 +00:00
Elena Demikhovsky
5cd32afac4
AVX-512: Concat 4 128-bit vectors in one 512-bit vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 09:10:40 +00:00
Elena Demikhovsky
f58e414405
AVX-512: Handled extractelement from mask vector;
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Added VMOSHDUP/VMOVSLDUP shuffle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 11:29:27 +00:00
Elena Demikhovsky
a6269ee5fb
AVX-512: fixed shuffle lowering
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in case of BLEND and added VSHUFPS patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 06:11:18 +00:00
Elena Demikhovsky
92bfb54770
AVX-512: Added shuffle instructions -
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VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
single and double forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 12:45:35 +00:00
Elena Demikhovsky
41f7baf181
AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25 12:54:30 +00:00
Craig Topper
0163356ad1
Don't use v16i32 for load pattern matching. All 512-bit loads are cated to v8i64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 06:07:34 +00:00
Craig Topper
d36e1efa4b
Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 08:38:25 +00:00
Craig Topper
46ceaf4ba6
Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 07:30:51 +00:00
Elena Demikhovsky
fac4a4eb7d
AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.
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Added a test for shuffles using VPERM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-11 07:55:09 +00:00
