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13814 Commits

Author SHA1 Message Date
Nick Lewycky
7f0170c197 Don't attempt to add 'nsw' when intermediate instructions had no such guarantee. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-14 03:41:33 +00:00
Nick Lewycky
daf27ea899 Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis 
when combining add and sub instructions. Patch by Pranav Bhandarkar!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-14 01:45:19 +00:00
Eli Friedman
9a0f436da2 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-13 17:06:34 +00:00
Bob Wilson
7dcd04abe0 Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-13 05:14:55 +00:00
Eli Friedman
f03bb260c9 Move "atomic" and "volatile" designations on instructions after the opcode 
of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 22:50:01 +00:00
Bruno Cardoso Lopes
53cae1362d The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 21:48:26 +00:00
Akira Hatanaka
5c21c9e78e Define unaligned load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 21:30:06 +00:00
Owen Anderson
0d09499cf3 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 20:36:11 +00:00
Owen Anderson
a211c2c7e9 Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 19:42:45 +00:00
Akira Hatanaka
11abf5bca9 Test case for 137484 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 18:12:06 +00:00
Jim Grosbach
7a8729effc Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:43:31 +00:00
Jim Grosbach
46c38aff89 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:01:02 +00:00
Benjamin Kramer
0d46ccfc5c MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 01:51:29 +00:00
Dan Gohman
126a54f1fa Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result 
is returned through a bitcast.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137402 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 00:36:31 +00:00
Dan Gohman
a7f7db2ebd Don't let arbitrary calls disrupt nested retain+release pairs if 
the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 00:26:31 +00:00
Jim Grosbach
29e7b7deb4 Clean up formatting a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:57:17 +00:00
Jim Grosbach
857e1a7b3f ARM vector compare to zero instruction assembly parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:51:13 +00:00
Andrew Trick
30039de2e9 A slew of unit tests for the recent LoopInfo::updateUnloop feature 
checked in at r137276 and r137341.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137385 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:38:09 +00:00
Andrew Trick
b1831c6640 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:36:16 +00:00
Akira Hatanaka
9029cf20e1 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:42:31 +00:00
Jim Grosbach
c69c26d95e Fix tests per now-correct encoding as of r137371. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:31:48 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:18:00 +00:00
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Bruno Cardoso Lopes
ef8d6999f3 Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:44 +00:00
Bruno Cardoso Lopes
ec91640997 Fix the test added by Nadav in r137308. Make it more strict: 
1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:35 +00:00
Jim Grosbach
2ef8241ce7 ARM STRHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:39:41 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Owen Anderson
9fe72bcd37 Improve operand validation for Thumb2 addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Jim Grosbach
961afdf1b6 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:43:42 +00:00
Jim Grosbach
534de6cad8 ARM STRB assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:42:58 +00:00
Jim Grosbach
c15bd92d2f Fix a copy/paste error so that LDRB(register) actually gets tested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:34:23 +00:00
Jim Grosbach
f91c14920c ARM STR(register) assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:26:17 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
59353b436a Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:59:13 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:07:11 +00:00
Jim Grosbach
f8fce711e8 ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:35:48 +00:00
Nadav Rotem
5e742a3e1b [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 16:41:21 +00:00
Chris Lattner
7eba85eb86 add missing colon, thanks peter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 16:15:10 +00:00
Chris Lattner
f4ea68fa5a fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
5f1d8abf75 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
a5134a0ea3 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:41 +00:00
Eli Friedman
586272d67c Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 01:48:05 +00:00