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2 Commits

Author SHA1 Message Date
Tim Northover
1a8adcb569 AArch64/ARM64: add another set of tests from AArch64 
Another batch with no code changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206381 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-16 11:53:07 +00:00
Amara Emerson
2f21452ba1 [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-24 08:28:24 +00:00