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5 Commits

Author SHA1 Message Date
Tom Stellard
3986785046 R600/SI: Use -verify-machineinstrs for most tests 
We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:46 +00:00
Vincent Lejeune
bb25a01d23 R600: Non vector only instruction can be scheduled on trans unit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:46 +00:00
Michel Danzer
b89f197713 R600/SI: Add pattern for xor of i1 
Fixes two recent piglit regressions with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188559 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 16:19:31 +00:00
Aaron Watry
1842ec4d9f R600/SI: Expand xor v2i32/v4i32 
Add test cases for both vector sizes on SI and also add v2i32 test for EG.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 13:55:52 +00:00
Tom Stellard
19301d5d12 R600: Expand vector or, shl, srl, and xor nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 17:21:31 +00:00