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18 Commits

Author SHA1 Message Date
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Jim Grosbach
e30171ba0c Add some tests for all-lanes VLD1 parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:37:38 +00:00
Jim Grosbach
e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 23:19:15 +00:00
Jim Grosbach
e052b9afa1 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:32:59 +00:00
Jim Grosbach
c73d73eb88 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 00:06:50 +00:00
Jim Grosbach
399cdca4d2 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:14:01 +00:00
Jim Grosbach
5921675ff5 ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:26:05 +00:00
Jim Grosbach
12431329d6 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 22:16:58 +00:00
Jim Grosbach
224180e81b Assembly parsing for 4-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Jim Grosbach
6b09c77b7a ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 15:04:25 +00:00
Jim Grosbach
0ebefdf834 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 21:43:51 +00:00
Owen Anderson
f0ea0f2b15 Add correct encodings for the rest of the vld instructions that we generate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 20:40:59 +00:00
Owen Anderson
cf667be17b Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:24:55 +00:00
Owen Anderson
d9aa7d30aa Add correct NEON encodings for the "multiple single elements" form of vld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:05:05 +00:00