Commit Graph

41614 Commits

Author SHA1 Message Date
Devang Patel
4fe0fe8b49 splitLoop does not handle split condition EQ.
Fixes PR 2805


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56321 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 23:45:14 +00:00
Dan Gohman
3589308f37 Address-mode folding for X86FastISel. It's pretty basic, but it
catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56320 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 23:23:44 +00:00
Bill Wendling
670ed09238 Decrementing the iterator here could be wrong if the worklist is empty after the "erase".
Thanks to Ji Young Park for the patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56316 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 23:04:18 +00:00
Devang Patel
3d0a9a371c Try to place hoisted instructions befoe icmp instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 22:50:42 +00:00
Evan Cheng
841ee1a12b Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56314 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 22:38:47 +00:00
Dan Gohman
1fbc3cd674 Simplify this code. The FastISel class has its own TD member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56311 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 18:26:43 +00:00
Dan Gohman
e251b1529f Don't consider instructions with implicit physical register
defs to be necessarily live.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56310 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 18:22:32 +00:00
Tanya Lattner
6a0fd93547 Upgrade doxygen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56308 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 16:32:28 +00:00
Dan Gohman
ee2e403545 Add a new "fast" scheduler. This is currently basically just a
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 16:26:26 +00:00
Evan Cheng
bc4707a255 Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56303 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 07:54:21 +00:00
Evan Cheng
057d0c3535 Duh. Default to ARMCC::AL (always).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56301 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 07:28:19 +00:00
Evan Cheng
6d63a72858 Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56300 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 07:27:23 +00:00
Evan Cheng
3f7eb8eba0 Cosmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56299 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 07:24:33 +00:00
Dan Gohman
b5b6ec6488 FastISel: For calls, prefer using the callee's address as a constant
over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.

This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56292 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 21:18:49 +00:00
Dale Johannesen
91aac1015e Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 21:13:11 +00:00
Evan Cheng
870e4bef41 Unallocatable registers do not have live intervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56287 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 18:36:25 +00:00
Devang Patel
48fbc2d39b Do not hoist instruction above branch condition. The instruction may use branch condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56286 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 18:21:49 +00:00
Devang Patel
00622952ce Do not ignore iv uses outside the loop.
This one slipped through cracks very well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56284 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 17:53:47 +00:00
Devang Patel
442b1aa94b Fix comments, help messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56282 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 16:01:39 +00:00
Dan Gohman
59932584a8 Don't worry about clobbering physical register defs that aren't used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56281 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 15:25:49 +00:00
Evan Cheng
7fd7ca4e7f Fix addrmode1 instruction encodings; fix bx_ret encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 07:53:38 +00:00
Evan Cheng
29c57c34ef Specify instruction encoding using range list to avoid endianess issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 07:16:21 +00:00
Evan Cheng
bc95b23156 Add instruction names as comments to InstBits entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56275 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 06:29:52 +00:00
Dan Gohman
682d5a8834 Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56270 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 01:39:10 +00:00
Dan Gohman
d3ead4329e Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56268 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 00:43:24 +00:00
Bill Wendling
7795932d41 Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
function with appropriate parameters. This allows us to support blocks on PPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56267 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 00:30:57 +00:00
Devang Patel
d9424edf94 Fix cut-n-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56265 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 00:01:04 +00:00
Evan Cheng
1cd332725f When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56258 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 23:12:11 +00:00
Devang Patel
f94474161f Remove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56256 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 22:26:44 +00:00
Devang Patel
2d7551ced2 Add -O1, -O2 and -O3 that matches llvm-gcc's -O1, -O2 and -O3 respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56255 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 22:25:14 +00:00
Dan Gohman
50284d81f8 Change SelectionDAG::getConstantPool to always set the alignment of the
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56253 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 22:05:41 +00:00
Bill Wendling
056292fd73 Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:48:12 +00:00
Dan Gohman
aed48bfee8 Include the alignment value when displaying ConstantPoolSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56250 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:18:22 +00:00
Bill Wendling
9468a9b6be - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:12:30 +00:00
Dan Gohman
05ae98346a Fix these comments to reflect current reality. Surprisingly,
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56248 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 20:45:53 +00:00
Dan Gohman
70ff4cf1ba Finally re-apply r46959. This is made feasible by the combination
of r56230, r56232, and r56246.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56247 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 18:52:57 +00:00
Dan Gohman
81b28ceab6 Improve instcombine's handling of integer min and max in two ways:
- Recognize expressions like "x > -1 ? x : 0" as min/max and turn them
   into expressions like "x < 0 ? 0 : x", which is easily recognizable
   as a min/max operation.
 - Refrain from folding expression like "y/2 < 1" to "y < 2" when the
   comparison is being used as part of a min or max idiom, like
   "y/2 < 1 ? 1 : y/2". In that case, the division has another use, so
   folding doesn't eliminate it, and obfuscates the min/max, making it
   harder to recognize as a min/max operation.

These benefit ScalarEvolution, CodeGen, and anything else that wants to
recognize integer min and max.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 18:46:06 +00:00
Evan Cheng
19a341acb8 AllocateRWXMemory -> AllocateRWX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56244 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 17:28:18 +00:00
Dan Gohman
793df075c9 FCmpInst predicates UNO, ORD, FALSE, and TRUE are commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56243 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 16:44:00 +00:00
Bill Wendling
10dd39b1e8 Fix test to account for no more whitespace and that one of the matches is the
"declare" statement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56241 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 06:40:04 +00:00
Bill Wendling
4fc2b73eb3 Remove space that was forgotten.`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56240 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 06:30:47 +00:00
Dan Gohman
1937e2f6ca Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
are not enabled. Instead just omit the tail call flag when calls are
created.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56235 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 01:42:28 +00:00
Dan Gohman
c7e42fd5b2 Fix spacing in the grep line for this test, following the recent
SCEV-whitespace changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56234 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 01:37:08 +00:00
Dan Gohman
fb2bbbe786 Re-enables the new vector select in the bitcode reader, by modifying the
bitcode reader/writer as follows:

- add and use new bitcode FUNC_CODE_INST_VSELECT to handle the llvm
select opcode using either i1 or [N x i1] as the selector.
- retain old BITCODE FUNC_CODE_INST_SELECT in the bitcode reader to
handle select on i1 for backwards compatibility with existing bitcode
files.
- re-enable the vector-select.ll test program.

Also, rename the recently added bitcode opcode FUNC_CODE_INST_VCMP to
FUNC_CODE_INST_CMP2 and make the bitcode writer use it to handle
fcmp/icmp on scalars or vectors. In the bitcode writer, use
FUNC_CODE_INST_CMP for vfcmp/vicmp only. In the bitcode reader, have
FUNC_CODE_INST_CMP handle icmp/fcmp returning bool, for backwards
compatibility with existing bitcode files.

Patch by Preston Gurd!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56233 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 01:01:33 +00:00
Dan Gohman
fd6edef87b Teach ScalarEvolution to consider loop preheaders in the search for
an if statement that guards a loop, to allow indvars to avoid smax
operations in more situations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56232 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 22:18:04 +00:00
Owen Anderson
99500aeb7c Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 22:00:38 +00:00
Dan Gohman
ad7321f58a Teach LSR to optimize away SMAX operations for tripcounts in common
cases.  See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56230 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 21:22:06 +00:00
Devang Patel
89e9ed3795 Extract optimization pass selection code from llvm-gcc into a separate routine.
This can be used by other stand alone tools, such as 'opt'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56229 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 21:13:42 +00:00
Bruno Cardoso Lopes
b3d7299694 Fixed Bug 2751
http://llvm.org/bugs/show_bug.cgi?id=2751

Abicall was enabled even when static code model was provided 
in the command line.
The correct behavior is to disable abicall when static is
specified.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56228 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 21:06:55 +00:00
Dan Gohman
5eb0cecbc5 Re-enable SelectionDAG CSE for calls. It matters in the case of
libcalls, as in this testcase on ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56226 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 19:46:03 +00:00