Misha Brukman
ed36fd8da6
Made the register and immediate versions of instructions consecutive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6439 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 19:14:01 +00:00
Misha Brukman
6ddd9d87a7
One of the first major changes to make the work of JITting easier: adding
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annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:32:38 +00:00
Chris Lattner
3501feab81
Rename MachineInstrInfo -> TargetInstrInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-14 22:00:31 +00:00
Chris Lattner
9a8e4121aa
Remove all traces of the "Opcode Mask" field in the MachineInstr class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4359 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-28 21:17:20 +00:00
Chris Lattner
232c3be0b5
Fix misspelling
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4276 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 01:43:26 +00:00
Vikram S. Adve
e0048667dd
Don't mark JMPLCALL and JMPLRET as branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4132 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-13 00:22:32 +00:00
Vikram S. Adve
ac67006bed
Return address register should be marked as "result" for the JMPL instruction
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since it is defined by the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3966 91177308-0d34-0410-b5e6-96231b3b80d8
2002-09-28 17:00:15 +00:00
Vikram S. Adve
97da3649dd
BA has only one argument.
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Added LDFSR, LDXFSR, STFSR and STXFSR.
Fixed operands info for RDCCR, WRCCR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2835 91177308-0d34-0410-b5e6-96231b3b80d8
2002-07-08 23:25:17 +00:00
Vikram S. Adve
585612e556
Change latencies for Load, Store and Branch instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1965 91177308-0d34-0410-b5e6-96231b3b80d8
2002-03-24 03:33:53 +00:00
Vikram S. Adve
c9c6aa0445
Change latency of SETX to improve schedule -- just a hack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1304 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-14 15:54:44 +00:00
Ruchira Sasanka
d63aaaaabe
Added M_PSEUDO_FLAG for SETX .. instr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1301 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-14 15:35:13 +00:00
Vikram S. Adve
b7f06f46a1
Fixed instruction information for RDCCR and WRCCR.
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Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1120 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-04 19:34:49 +00:00
Ruchira Sasanka
3839e6e309
Added code to support correct saving of %ccr across calls
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1111 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-03 19:59:59 +00:00
Vikram S. Adve
c7b2e5c81e
Add SETX instruction for 64-bit constants.
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Add M_CC_FLAG for many instructions that use int or fp CC registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1006 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-28 21:41:01 +00:00
Vikram S. Adve
1d86cc06dc
Added SAVE and RESTORE. Duplicated JMPL into JMPLCALL and JMPLRET,
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which have the same opcode and operands but different flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@938 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-22 13:32:55 +00:00
Vikram S. Adve
6e64ef4008
Change latency of setuw and setsw to 2 cycles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@681 91177308-0d34-0410-b5e6-96231b3b80d8
2001-09-30 23:46:57 +00:00
Chris Lattner
9a3d63bcbe
Seperate instruction definitions into new SparcInstr.def file
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Move contents of SparcMachineInstrDesc[] out of SparcInternals.h
into Sparc.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@644 91177308-0d34-0410-b5e6-96231b3b80d8
2001-09-19 15:56:23 +00:00