Commit Graph

68427 Commits

Author SHA1 Message Date
Craig Topper
8a0d1c8f06 [C++11] Make use of 'nullptr' in TableGen library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 04:50:04 +00:00
Craig Topper
725011e72f [C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205829 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 04:20:00 +00:00
David Majnemer
e4d89ec8de WinCOFF: Emit common symbols as specified in the COFF spec
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.

Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.

Reviewers: Bigcheese, rafael, rnk

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 22:33:40 +00:00
Matt Arsenault
1507319299 Bug 19348: Check for legal ExtLoad operation before folding
(aext (zextload x)) -> (aext (truncate (*extload x)))

Patch by Stanislav Mekhanoshin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205805 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 21:40:37 +00:00
Sebastian Pop
a83f78786e divide by the result of the gcd
used to fail with 'Step should divide Start with no remainder.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205802 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 21:21:13 +00:00
Sebastian Pop
89e11b110a handle special cases when findGCD returns 1
used to fail with 'Step should divide Start with no remainder.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205801 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 21:21:10 +00:00
Sebastian Pop
d541e6e6ea in findGCD of multiply expr return the gcd
we used to return 1 instead of the gcd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205800 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 21:21:05 +00:00
Juergen Ributzka
c6a7502a80 [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.
This implements the target-hooks for ARM64 to enable constant hoisting.

This fixes <rdar://problem/14774662> and <rdar://problem/16381500>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 20:39:59 +00:00
Duncan P. N. Exon Smith
861e4db905 RegAlloc: Account for a variable entry block frequency
Until r197284, the entry frequency was constant -- i.e., set to 2^14.
Although current ToT still has a constant entry frequency, since r197284
that has been an implementation detail (which is soon going to change).

  - r204690 made the wrong assumption for the CSRCost metric.  Adjust
    callee-saved register cost based on entry frequency.

  - r185393 made the wrong assumption (although it was valid at the
    time).  Update SpillPlacement.cpp::Threshold to be relative to the
    entry frequency.

Since ToT still has 2^14 entry frequency, this should have no observable
functionality change.

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205789 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 19:18:56 +00:00
Hal Finkel
c0c10f20a2 [PowerPC] Don't return false from PPC::isVSLDOIShuffleMask
PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.

Noticed by inspection; no test case (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 19:00:27 +00:00
Kevin Enderby
9143956488 Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.

This:
	vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

	vld3.16	{d0[], d1[], d2[]}, [r4]!

rdar://16531387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 18:00:52 +00:00
Duncan P. N. Exon Smith
bd382db782 Verifier: Give the right message for bad atomic loads
Talk about load (not store) on an invalid atomic load.

<rdar://problem/16287567>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 17:07:44 +00:00
Diego Novillo
35d647b6f3 Add -pass-remarks flag to 'opt'.
Summary:
This adds support in 'opt' to filter pass remarks emitted by
optimization passes. A new flag -pass-remarks specifies which
passes should emit a diagnostic when LLVMContext::emitOptimizationRemark
is invoked.

This will allow the front end to simply pass along the regular
expression from its own -Rpass flag when launching the backend.

Depends on D3227.

Reviewers: qcolombet

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D3291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 16:42:38 +00:00
Diego Novillo
ccbf1d2a05 Add support for optimization reports.
Summary:
This patch adds backend support for -Rpass=, which indicates the name
of the optimization pass that should emit remarks stating when it
made a transformation to the code.

Pass names are taken from their DEBUG_NAME definitions.

When emitting an optimization report diagnostic, the lack of debug
information causes the diagnostic to use "<unknown>:0:0" as the
location string.

This is the back end counterpart for

http://llvm-reviews.chandlerc.com/D3226

Reviewers: qcolombet

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D3227

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 16:42:34 +00:00
NAKAMURA Takumi
60db02b6fe X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 15:28:50 +00:00
Tim Northover
362090adf5 ARM64: fix fmsub patterns which assumed accum operand was first
Confusingly, the NEON fmla instructions put the accumulator first but the
scalar versions put it at the end (like the fma lib function & LLVM's
intrinsic).

This should fix PR19345, assuming there's only one issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 12:23:51 +00:00
Elena Demikhovsky
dbcb670605 AVX-512: Added fp_to_uint and uint_to_fp patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 07:24:02 +00:00
Andrew Trick
3c1f2eb75d Fix a (legacy) PassManager crash that occurs when a ModulePass
indirectly requires a function analysis.

This bug was reported by Jason Kim. He included a test case here:
http://reviews.llvm.org/D3312

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 03:40:34 +00:00
David Majnemer
2424511b6f X86: Split the relocation selection up
Before, we would have conditional operators where one side of the
operator would be of type RelocationTypeAMD64 and the other is of type
RelocationTypeI386.  GCC would noisly warn with -Wenum-compare
diagnostic.

Instead, refactor the code so it is more like the X86 ELF object writer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 02:15:13 +00:00
Jim Grosbach
ba1895c16d Tidy up comments a bit.
Punctuation, grammar, formatting, etc..

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205749 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 23:47:23 +00:00
Jim Grosbach
8e492b1711 ARM64: Range based for loop in ARM64PromoteConstant pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 23:47:21 +00:00
Jim Grosbach
2ed715793d ARM64: Clean up file header comment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 23:14:38 +00:00
David Majnemer
de6256c938 obj2yaml: Use the correct relocation type for different machine types
The IO normalizer would essentially lump I386 and AMD64 relocations
together.  Relocation types with the same numeric value would then get
mapped in appropriately.

For example:
IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric
value of one.  We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions
of object files with a machine type of IMAGE_FILE_MACHINE_AMD64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205746 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 23:12:20 +00:00
Reed Kotler
bb0572a5d1 Reverting commit r205628 due to mips64 issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 22:11:40 +00:00
Andrew Trick
7f72633547 Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time.
Fixes PR16365 - Extremely slow compilation in -O1 and -O2.

The SD scheduler has a quadratic implementation of load clustering
which absolutely blows up compile time for large blocks with constant
pool loads. The MI scheduler has a better implementation of load
clustering. However, we have not done the work yet to completely
eliminate the SD scheduler. Some benchmarks still seem to benefit from
early load clustering, although maybe by chance.

As an intermediate term fix, I just put a nice limit on the number of
DAG users to search before finding a match. With this limit there are no
binary differences in the LLVM test suite, and the PR16365 test case
does not suffer any compile time impact from this routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 21:29:22 +00:00
Tom Stellard
1d8c7eb225 R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:45 +00:00
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:41 +00:00
Tom Stellard
dd2d430352 R600: Replace dyn_cast + assert with cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205730 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:31:13 +00:00
Matt Arsenault
939ec8514d Use std::swap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205723 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 16:44:26 +00:00
Matt Arsenault
e3e086ea00 Use .data() instead of &x[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 16:44:24 +00:00
Eric Christopher
fc3588b336 Invert the option to enable debug info verification. No functional
change outside of the command line to enable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205713 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 13:55:21 +00:00
Eric Christopher
9a764dfa92 Handle vlas during inline cost computation if they'll be turned
into a constant size alloca by inlining.

Ran a run over the testsuite, no results out of the noise, fixes
the testcase in the PR.

PR19115.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 13:36:21 +00:00
Eric Christopher
231ed9dd9c Add NDEBUG markers around debug only function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 12:46:30 +00:00
Eric Christopher
c75aecc473 Add debug location information to the vectorizer debug statements.
Patch by Zinovy Nis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205705 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 12:32:17 +00:00
Craig Topper
34bc6b6e78 [C++11] Make use of 'nullptr' in the Support library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 04:17:22 +00:00
Elena Demikhovsky
ec8891fdde Changes in IntelJITEventListener - By Arch Robinson
- take->release: LLVM has moved to C++11.  MockWrapper became an instance of unique_ptr.

   - method symbol_iterator::increment disappeared recently, in this revision:

     r200442 | rafael | 2014-01-29 20:49:50 -0600 (Wed, 29 Jan 2014) | 9 lines

Simplify the handling of iterators in ObjectFile.

None of the object file formats reported error on iterator increment. In
retrospect, that is not too surprising: no object format stores symbols or
sections in a linked list or other structure that requires chasing pointers.
As a consequence, all error checking can be done on begin() and end().

This reduces the text segment of bin/llvm-readobj in my machine from 521233 to
518526 bytes.

My change mimics the change that the revision made to lib/DebugInfo/DWARFContext.cpp .

    - const_cast: Shut up a warning from gcc.

I ran unittests/ExecutionEngine/JIT/Debug+Asserts/JITTests to make sure it worked.

- Arch



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-06 11:08:33 +00:00
David Blaikie
1c41705d34 DebugInfo: Support namespace aliases as DW_TAG_imported_declaration instead of DW_TAG_imported_module
I really should read the spec more often (and test GCC more often too).
I just assumed that namespace aliases would be the same as using
directives, except with a name. But apparently that's not how the DWARF
standards suggests they be implemented. DWARF4 provides an example and
other non-normative text suggesting that namespace aliases be
implemented by named imported declarations intsead of named imported
modules.

So be it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-06 06:29:01 +00:00
Argyrios Kyrtzidis
20384a5583 [Support] Modify LockFileManager::waitForUnlock() to return info about how the lock was released.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-06 03:19:31 +00:00
David Blaikie
ec37734d3c Remove unused parameter
Also update a few null pointers in this function to be consistent with
new null pointers being added.

Patch by Robert Matusewicz!

Differential Revision: http://reviews.llvm.org/D3123

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205682 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 23:33:25 +00:00
Saleem Abdulrasool
fa254cb46c AsmParser: add a warning for compatibility parsing
This adds a warning when linker_private or linker_private_weak is provided and
we handle it in a compatible manner.

Suggested by Chris Lattner!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 22:42:53 +00:00
David Blaikie
b29a2b0c4c MachineInstr: introduce explicit_operands and implicit_operands ranges
Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 22:42:04 +00:00
Saleem Abdulrasool
2a65dd3101 ARM: consolidate MachO checks for ARM asm parser
This consolidates the duplicated MachO checks in the directive parsing for
various directives that are unsupported for Mach-O.  The error message change is
unimportant as this restores the behaviour to that prior to the addition of the
new directive handling.  Furthermore, use a more direct check for MachO
targeting rather than an indirect feature check of the assembler.

Also simplify the test execution command to avoid temporary files.  Further more,
perform the check in both object and assembly emission.

Whether all non-applicable directives are handled is another question.  .fnstart
is marked as being unsupported, however, the complementary .fnend is not.  The
additional unwinding directives are also still honoured.  This change does not
change that, though, it would be good to validate and mark them as being
unsupported if they are unsupported for the MachO emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 22:09:51 +00:00
David Blaikie
b4074c010b Simplify compression API by compressing into a SmallVector rather than a MemoryBuffer
This is the other half of r205676.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 21:53:04 +00:00
David Blaikie
b206103abc Simplify compression API by decompressing into a SmallVector rather than a MemoryBuffer
This avoids an extra copy during decompression and avoids the use of
MemoryBuffer which is a weirdly esoteric device that includes unrelated
concepts like "file name" (its rather generic name is a bit misleading).

Similar refactoring of zlib::compress coming up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 21:26:44 +00:00
Saleem Abdulrasool
48ee81c679 AsmParser: restore LLVM IR compatibility for linker_private{,_weak}
This restores the linker_private and linker_private_weak lexemes to permit
translation of the deprecated lexmes.  The behaviour is identical to the bitcode
handling: linker_private and linker_private_weak are handled as if private had
been specified.  This enables compatibility with IR generated by LLVM 3.4.

Reported on IRC by ki9a!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 20:51:58 +00:00
David Blaikie
2c5f72b629 Fixing typo.
Differential Revision: http://reviews.llvm.org/D3154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 20:30:31 +00:00
Hal Finkel
d260b1ba81 [PowerPC] Remove unused TM member variable to unbreak build
Fix "error: private field 'TM' is not used [-Werror,-Wunused-private-field]"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 00:16:28 +00:00
Hal Finkel
e6a5b33e6e [PowerPC] Adjust load/store costs in PPCTTI
This provides more realistic costs for the insert/extractelement instructions
(which are load/store pairs), accounts for the cheap unaligned Altivec load
sequence, and for unaligned VSX load/stores.

Bad news:
MultiSource/Applications/sgefa/sgefa - 35% slowdown (this will require more investigation)
SingleSource/Benchmarks/McGill/queens - 20% slowdown (we no longer vectorize this, but it was a constant store that was scalarized)
MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 - 2% slowdown

Good news:
SingleSource/Benchmarks/Shootout/ary3 - 54% speedup
SingleSource/Benchmarks/Shootout-C++/ary - 40% speedup
MultiSource/Benchmarks/Ptrdist/ks/ks - 35% speedup
MultiSource/Benchmarks/FreeBench/neural/neural - 30% speedup
MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt - 20% speedup

Unfortunately, estimating the costs of the stack-based scalarization sequences
is hard, and adjusting these costs is like a game of whac-a-mole :( I'll
revisit this again after we have better codegen for vector extloads and
truncstores and unaligned load/stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 23:51:18 +00:00
Hal Finkel
cef9f7ef27 [PowerPC] PPCTTI Cleanup
Remove the declaration of an unimplemented function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 23:51:11 +00:00
Andrew Trick
0610fb407e Minor change to StackMapLiveness DEBUG output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205656 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 23:49:35 +00:00