Vincent Lejeune
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8f9fbd67c3
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R600: Support schedule and packetization of trans-only inst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-06-29 19:32:43 +00:00 |
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Vincent Lejeune
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512119770e
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R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-06-05 20:27:35 +00:00 |
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Vincent Lejeune
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96fe0be43b
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R600: use capital letter for PV channel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-06-03 15:44:35 +00:00 |
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Vincent Lejeune
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76fc2d077f
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R600: Use bottom up scheduling algorithm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-05-17 16:50:56 +00:00 |
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Vincent Lejeune
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92f24d403f
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R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-05-02 21:52:30 +00:00 |
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Michel Danzer
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21675c8ab0
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R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-03-22 15:24:16 +00:00 |
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Tom Stellard
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f98f2ce29e
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Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-11 21:25:42 +00:00 |
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