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8fb06b3e8f
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9 Commits

Author SHA1 Message Date
Nadav Rotem
8fb06b3e8f Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 20:31:33 +00:00
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 20:48:40 +00:00
Bob Wilson
f20700ca77 SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:38:28 +00:00
Bob Wilson
7aaf5bf3db Allow more cases of undef shuffle indices and add tests for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 05:54:34 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this 
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 15:18:27 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 00:09:15 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00