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5 Commits

Author SHA1 Message Date
NAKAMURA Takumi
ddbfbcf72e test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127732 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-16 13:52:38 +00:00
Dan Gohman
36a0947820 Eliminate more uses of llvm-as and llvm-dis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 23:54:48 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:49:04 +00:00
Evan Cheng
687bcb2be0 Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50837 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-07 22:59:08 +00:00
Dan Gohman
4106f3714e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40015 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 20:23:34 +00:00