Commit Graph

5 Commits

Author SHA1 Message Date
Bill Schmidt
11729224bf [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
This is a preliminary patch for fast instruction selection on
PowerPC.  Code generation can differ between DAG isel and fast isel.
Existing tests that specify -O0 were written to expect DAG isel.  Make
this explicit by adding -fast-isel=false to the tests.

In some cases specifying -fast-isel=false produces different code even
when there isn't a fast instruction selector specified.  This is
because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel
object exists.  Thus disabling fast isel can actually produce less
conservative code.  Because of this, some of the expected code
generation in the -O0 tests needs to be adjusted.

In particular, handling of function arguments is less conservative
with -fast-isel=false (see isOnlyUsedInEntryBlock() in
SelectionDAGBuilder.cpp).  This results in fewer stack accesses and,
in some cases, reduced stack size as uselessly loaded values are no
longer stored back to spill locations in the stack.

No functional change with this patch; test case adjustments only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 20:23:34 +00:00
Hal Finkel
3249729043 Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:

  1. The spilling code was inefficient (using two instructions, and add and a
     load, when just one would do)

  2. The code assumed that r0 would always be available (true for now, but this
     will change)

The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17 04:43:44 +00:00
Bill Schmidt
e0bc37579b Add -mattr=+altivec and remove XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165666 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 22:25:11 +00:00
Bill Schmidt
3a55b64e5e XFAIL for all targets pending investigation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 21:52:10 +00:00
Bill Schmidt
26160f4e64 When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0.  However, there are two flavors of
GPR0 defined by the target:  the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0).  The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.

This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 21:25:01 +00:00