Commit Graph

10 Commits

Author SHA1 Message Date
Joey Gouly
bad8d4ca59 [ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:19:24 +00:00
Tim Northover
a10c01a6c6 ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.

This patch makes use of that quirk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 09:20:36 +00:00
Tim Northover
40d0492cde Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 18:37:33 +00:00
Tim Northover
d59fc0af0a ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 14:48:48 +00:00
Lang Hames
dfccd9ee98 Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult
should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP.

Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to
ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash
during isel.

<rdar://problem/14074644>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 18:36:42 +00:00
Eli Friedman
17569fe05b Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:02:33 +00:00
Eli Friedman
331120b1a4 Some legalization fixes for atomic load and store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 21:20:49 +00:00
Eli Friedman
981a010c09 Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 02:23:42 +00:00
Eli Friedman
4136d23c48 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:33:24 +00:00
Eli Friedman
069e2ed794 Atomic load/store on ARM/Thumb.
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 02:59:24 +00:00