Owen Anderson
07700d486e
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:59:41 +00:00
Bruno Cardoso Lopes
41dfabb0e3
Move non-intruction patterns to a more appropriate place!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:51:24 +00:00
Owen Anderson
63553c77cd
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:17:09 +00:00
Nicolas Geoffray
1c36ba50ac
Remove premature previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-28 14:52:51 +00:00
Nicolas Geoffray
c98da24bed
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-28 13:07:57 +00:00
Benjamin Kramer
2753ae314f
Silence GCC warnings and make an array const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-27 17:36:14 +00:00
Owen Anderson
f1eab597b2
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Owen Anderson
d7568e1c35
Correct encoding of BL with immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 22:54:51 +00:00
Jim Grosbach
4af54a461f
ARM assembly parsing tweak for pldw.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 22:21:51 +00:00
Owen Anderson
9f7e831994
Spelling fail.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:47:57 +00:00
Jim Grosbach
89df996ab2
Thumb2 assembler parsing and encoding of IT instruction.
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This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:43:41 +00:00
Eli Friedman
43f51aeca8
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:21:21 +00:00
Owen Anderson
2b568fb3ce
Fix ARM codegen breakage caused by r138653.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:12:37 +00:00
Owen Anderson
9ab0f25fc1
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d
Update for feedback from Jim.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15
ARMDisassembler: Always return a size, even when disassembling fails.
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This should fix PR10772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:09:22 +00:00
Kalle Raiskila
54f8a9f54d
Don't insert branch hint lables that are never used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 10:14:56 +00:00
Owen Anderson
9bd655dcde
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 06:19:51 +00:00
Craig Topper
8fd13b6de5
Fix disassembling of VCVTSD2SI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
Eli Friedman
069e2ed794
Atomic load/store on ARM/Thumb.
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I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 02:59:24 +00:00
Bruno Cardoso Lopes
f1a264232c
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 22:23:58 +00:00
Nick Lewycky
b210cbf692
Remove stray fullstop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:46:20 +00:00
Bruno Cardoso Lopes
6292eceea0
Add support for AVX 256-bit version of MOVDDUP!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes
06ef923d14
Make isMOVDDUP mask check more strict and update comments!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:40:34 +00:00
Owen Anderson
99906830e8
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 18:30:18 +00:00
Andrew Trick
b9ca5124f8
ARM fix for missing implicit operands on ldmia_ret.
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rdar://10005094: miscompile of 176.gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:50:53 +00:00
Andrew Trick
51972da576
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:40:54 +00:00
Jim Grosbach
0c49ac05cd
Explicitly disallow predication in Thumb1 assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:23:55 +00:00
Craig Topper
ebc1db0fac
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 08:11:01 +00:00
Craig Topper
ea03659d23
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
Bruno Cardoso Lopes
07b7f672a0
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 02:58:26 +00:00
Bruno Cardoso Lopes
e7461c0353
Add memory version of SHUFPD to mask decoding!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 02:58:21 +00:00
Evan Cheng
77eaaf0a0c
Hide -global-merge option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 01:22:49 +00:00
Evan Cheng
b8cfe4ff41
Add a command line option to disable global merge pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 01:00:36 +00:00
Evan Cheng
0f660260e6
Remove a out-of-place comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 00:54:42 +00:00
Bruno Cardoso Lopes
27831e5e6f
Create a section for non-instructions patterns in the beginning of the
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file, and move more code around!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:11 +00:00
Bruno Cardoso Lopes
9993499057
Move code around!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:09 +00:00
Bruno Cardoso Lopes
de79231468
Organize UNPCK* patterns, also add remaining for AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:06 +00:00
Bruno Cardoso Lopes
4cf4778ac4
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
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the missing ones for AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:04 +00:00
Bruno Cardoso Lopes
4724f25ed6
Organize and tidy up MOVDDUP section. Also update comments!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:02 +00:00
Bruno Cardoso Lopes
6140294363
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
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pattern for 128-bit AVX mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:59 +00:00
Bruno Cardoso Lopes
954d5eabb7
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
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explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:57 +00:00
Bruno Cardoso Lopes
af002d8405
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
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explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:55 +00:00
Owen Anderson
f44082091c
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:40:22 +00:00
Eli Friedman
f8f90f0174
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:33:28 +00:00
Jim Grosbach
b9d3ff8729
ARM asm backend initialize isThumbMode based on target triple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:27:35 +00:00
Jim Grosbach
4d23e99d2a
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:19:48 +00:00
Jim Grosbach
f69c804036
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:42:27 +00:00
Owen Anderson
12a1e3bbcb
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:35:46 +00:00
Jim Grosbach
72f39f8436
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:22:15 +00:00
Eli Friedman
4317fe1fc6
Fix whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:17:30 +00:00
Eli Friedman
327236cd6c
Basic x86 code generation for atomic load and store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 20:50:09 +00:00
Jim Grosbach
df9ce6bbc5
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
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rdar://10015134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 20:06:14 +00:00
Bruno Cardoso Lopes
356e988110
Mark VZEROALL as clobbering all YMM registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:48:33 +00:00
Jim Grosbach
f95aaf951b
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:19:42 +00:00
Evan Cheng
3e74d6fdd2
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Jim Grosbach
c7e0bb2325
Thumb add SP assembly syntax fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:04:27 +00:00
Jim Grosbach
5b81584f74
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
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Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:46:13 +00:00
Owen Anderson
e234d02204
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:21:43 +00:00
Richard Osborne
8f9c5cca4f
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
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variable sized alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 13:32:43 +00:00
Craig Topper
13894fa135
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 06:14:18 +00:00
Bruno Cardoso Lopes
d8b7dd5252
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
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permutations. Also tidy up some patterns and make them close to their
instruction definition!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 22:06:37 +00:00
Jim Grosbach
5aa29a0cff
Move ARM frame-unwinding EHABI handling a touch earlier.
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It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 21:32:34 +00:00
Jim Grosbach
d04f6a581c
[SU]XT[BH] are only available on ARMv6 and up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 20:53:08 +00:00
Evan Cheng
7801136b95
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 20:15:21 +00:00
Jim Grosbach
ec8b866434
Thumb parsing and encoding for SVC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 19:49:10 +00:00
Nick Lewycky
726ebd6ff3
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 19:01:24 +00:00
Jim Grosbach
803b1aa8ef
Thumb parsing and encoding for tSTRspi.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:39:41 +00:00
Jim Grosbach
1e84f19337
Thumb parsing and encoding for STM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:15:37 +00:00
Jim Grosbach
aa875f8c6f
Factor low reg checking into a helper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:13:04 +00:00
Owen Anderson
82265a2c72
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:45:18 +00:00
Jim Grosbach
cefe4c9c48
Clean up Thumb load/store multiple definitions.
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There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:41:15 +00:00
Owen Anderson
e732cb0043
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:37:32 +00:00
Craig Topper
a534780da0
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 04:36:33 +00:00
Bruno Cardoso Lopes
3bde6fe0df
Introduce a pass to insert vzeroupper instructions to avoid AVX to
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SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 01:14:17 +00:00
Jim Grosbach
04d55f1905
Thumb parsing and encoding for SBC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:55:58 +00:00
Jim Grosbach
934755ac04
Thumb parsing and encoding for RSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:47:13 +00:00
Owen Anderson
8e1e60b5f8
Reject invalid imod values in t2CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:44:04 +00:00
Owen Anderson
c6788c83b4
t2SMLAD is a four-register instruction, not a three-register one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe
Correct operand naming of t2USAT16 to allow proper decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:27:47 +00:00
Jim Grosbach
86b5d2b02d
Revert r138278 now that r138289 has fixed the root issue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:25:48 +00:00
Owen Anderson
2379fc235f
Match operand naming to allow correct decoding of t2LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:22:05 +00:00
Jim Grosbach
6dcafc0d0b
Improve error checking for tPUSH and tPOP register lists.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:17:34 +00:00
Owen Anderson
796c3659c9
Match operand names to provide correct decoding for Thumb2 SMULL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:16:48 +00:00
Owen Anderson
2c9f83533b
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:10:16 +00:00
Jim Grosbach
7260c6a4ea
Thumb assemmbly parsing diagnostic improvements for LDM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:01:07 +00:00
Benjamin Kramer
3c1fece071
X86: Add some operand types required to identify calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 22:55:32 +00:00
Jim Grosbach
5e8701002b
Temporarilly mark tMUL as not commutable.
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It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 22:00:18 +00:00
Owen Anderson
838130e3b9
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 21:34:00 +00:00
Bruno Cardoso Lopes
2ac8111159
Add support for breaking 256-bit int VETCC into two 128-bit ones,
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avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138271 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:31:04 +00:00
Bruno Cardoso Lopes
bde9f1b302
Add 128-bit AVX codegen for PCMP* family of integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:31:00 +00:00
Owen Anderson
357ec6850b
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:27:12 +00:00
Jim Grosbach
11e03e7c2d
Tighten up ARM reglist validation a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:50:36 +00:00
Owen Anderson
2cbf210450
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:22:06 +00:00
Jim Grosbach
a33b31be45
Clean up predicates on ARM target instruction aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:04:24 +00:00
Owen Anderson
b113ec55e8
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 17:56:58 +00:00
Benjamin Kramer
0dac82d92e
Cast through intptr_t, ISO C++ requires it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 02:22:42 +00:00
Chad Rosier
fea95c6bad
Remove the VMOVQQ pseudo instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:52:40 +00:00
Chad Rosier
bdc18572be
Remove VMOVQQQQ pseudo instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen
ac3656ed7a
Add <imp-def> operands to QQ and QQQQ stack loads.
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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:17:45 +00:00
Chad Rosier
e5038e191d
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:17:25 +00:00
Jim Grosbach
0780b6303b
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 23:24:36 +00:00
Akira Hatanaka
854a7db117
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
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needed for Mips32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:59:00 +00:00
Jim Grosbach
2c3f70e5d4
Thumb assembly parsing and encoding for NEG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:51:03 +00:00
Jim Grosbach
3a244bd8b3
Fix NEG alias
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:30:58 +00:00
Jim Grosbach
7a01069420
Be more lenient on tied operand matching for MUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
0c9acfcb50
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:27:29 +00:00
Jim Grosbach
7a32fa1c78
Update tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:19:48 +00:00
Jim Grosbach
88ae2bc6d5
Thumb assembly parsing and encoding for MUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:07:46 +00:00
Jim Grosbach
4ec6e888ec
Thumb assembly parsing and encoding for MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 20:46:54 +00:00
Jim Grosbach
73a1c2cea1
Tidy up. Tab character.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 20:30:19 +00:00
Jim Grosbach
b86e2dbf61
Tab characters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 19:41:46 +00:00
Jim Grosbach
1b7b68f087
Thumb assembly parsing and encoding for LSL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 19:29:25 +00:00
Jim Grosbach
05b0156734
Thumb assembly parsing and encoding for LDRSB and LDRSH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 19:17:58 +00:00
Jim Grosbach
38466309d5
Thumb assembly parsing and encoding for LDRH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 18:55:51 +00:00
Jim Grosbach
48ff5ffe9e
Thumb assembly parsing and encoding for LDRB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 18:49:59 +00:00
Jim Grosbach
67b95f902a
Thumb assembly parsing and encoding for LDR(literal).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 18:20:48 +00:00
Jim Grosbach
ecd8589683
Thumb assembly parsing and encoding for LDR(immediate) form T2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 18:13:48 +00:00
Jim Grosbach
2f7232efd5
Use helper function to check for low registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 17:57:22 +00:00
Jim Grosbach
60f91a3d95
Thumb assembly parsing and encoding for LDR(immediate) form T1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 17:55:24 +00:00
Jim Grosbach
c6d7c653c9
Add explanatory comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 16:52:32 +00:00
Kalle Raiskila
67a9b1fcc7
Have SPU backend use the external TCE scheduler, if the library is loaded as a
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module.
Patch by Pekka Jääskeläinen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 10:50:24 +00:00
Craig Topper
e004d941ec
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
863e0f25b7
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 02:23:56 +00:00
Benjamin Kramer
a67f14bf53
Make a bunch of symbols private.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 01:42:18 +00:00
Bruno Cardoso Lopes
df01610d6f
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
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instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 23:59:21 +00:00
Akira Hatanaka
5ac8547a41
Use subword loads instead of a 4-byte load when the size of a structure (or a
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piece of it) that is being passed by value is smaller than a word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 23:39:37 +00:00
Owen Anderson
78affc9ea1
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:31:17 +00:00
Owen Anderson
1dd56f05e1
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:15:25 +00:00
Owen Anderson
14090bf263
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:11:02 +00:00
Jim Grosbach
93b3eff623
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 21:50:53 +00:00
Akira Hatanaka
dbe9a31683
Make IsShiftedMask a static function rather than defining it in an
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anonymous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 20:07:42 +00:00
Jim Grosbach
0d1511c022
Thumb assembly parsing and encoding for CMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 18:08:29 +00:00
Jim Grosbach
11cca7a2ea
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 17:51:36 +00:00
Jim Grosbach
90b5a08e1f
ARM Thumb blx instruction fixup has same data range as bl.
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These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 16:57:50 +00:00
Jim Grosbach
5f687decc8
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 16:50:45 +00:00
Bruno Cardoso Lopes
44d12eb998
Clenup and fix encoding for Mips ins and ext instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 16:30:49 +00:00
Jim Grosbach
3ce23d3d87
Add missing 'break'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 16:08:39 +00:00
Richard Osborne
c4dcf323cc
Add intrinsics for SETEV, GETED, GETET.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 13:00:48 +00:00
Bruno Cardoso Lopes
24b90e2287
Cleanup vector logical ops in AVX and add use int versions for simple
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v2i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 02:11:34 +00:00
Jim Grosbach
2f815c0b50
Remove extraneous newline from operand print method. PR10569.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 23:23:07 +00:00
Jim Grosbach
421993f428
Clean up patterns for Thumb1 system instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 23:08:57 +00:00
Akira Hatanaka
667645f814
Changed definition of EXT and INS per Bruno's comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 22:59:46 +00:00
Jim Grosbach
395b453bed
Thumb assembly parsing and encoding for B.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 22:57:40 +00:00
Jim Grosbach
00f5d98205
Thumb assembly parsing and encoding for ASR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 22:49:09 +00:00
Bruno Cardoso Lopes
0dd80b0d69
Fix PR10688. Add support for spliting 256-bit vector shifts when the
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shift amount is variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 22:12:20 +00:00