Commit Graph

7067 Commits

Author SHA1 Message Date
Dan Gohman
97b52b2a88 Tweak this test to be a little less unusual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73808 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 00:40:56 +00:00
Dan Gohman
763bad1a2b Generalize isLoopGuardedByCond's checking to consider two
SCEVUnknowns with identical Instructions to be equal. This allows
it to analze cases such as the attached testcase, where the front-end
has cloned the loop controlling expression. Along with r73805, this
lets IndVarSimplify eliminate all the sign-extend casts in the
loop in the attached testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73807 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 00:35:32 +00:00
Dan Gohman
2781f30eac Re-apply r73718, now that the fix in r73787 is in, and add a
hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73793 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 23:23:27 +00:00
Evan Cheng
ae69a2a12b Enable arm pre-allocation load / store multiple optimization pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 23:17:27 +00:00
Evan Cheng
73a76736fb Revert 73718. It's breaking 254.gap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73783 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 21:15:06 +00:00
Dan Gohman
958e292c7a Don't (unconditionally) use getSCEVAtScope to simplify the step
expression in IVUsers, because in the case of a use of a non-linear
addrec outside of a loop, this causes the addrec to be evaluated as
a linear addrec.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73774 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 17:33:15 +00:00
Chris Lattner
79c740ff47 make jump threading handle lexically identical compare instructions
as if they were multiple uses of the same instruction.  This interacts
well with the existing loadpre that j-t does to open up many new jump
threads earlier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73768 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 16:27:56 +00:00
Eli Friedman
7e2242be71 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to
handle with an SSE2 instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73760 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 07:00:55 +00:00
Nick Lewycky
9683f18174 Teach jump threading to look at comparisons between phi nodes and non-constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73755 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 04:56:29 +00:00
Chris Lattner
6a35b40250 Improve tail call elim to move loads above readonly calls
when it allows forming a tail call.  Patch by Frits van
Bommel.  This implements PR4323.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73752 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 04:22:16 +00:00
Chris Lattner
849832c0fb part of PR4405: disable a contentious optimization for
strcmp -> memcmp when the lengths of the strings are unknown.

Patch by Nick Lewycky!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 04:17:36 +00:00
Eli Friedman
6b7bb42c36 Mark a few Thumb instructions commutable; just happened to spot this
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:43:08 +00:00
Chris Lattner
3ea4edce6a new testcase for rdar://6983634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 22:53:26 +00:00
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 20:37:15 +00:00
Dan Gohman
4658c9b4ea Generalize LSR's OptimizeSMax to handle unsigned max tests as well
as signed max tests. Along with r73717, this helps CodeGen avoid
emitting code for a maximum operation for this class of loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73718 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 20:23:18 +00:00
Dan Gohman
4e8a98519e Remove the code from IVUsers that attempted to handle
casted induction variables in cases where the cast
isn't foldable. It ended up being a pessimization in
many cases. This could be fixed, but it would require
a bunch of complicated code in IVUsers' clients. The
advantages of this approach aren't visible enough to
justify it at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73706 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 16:54:06 +00:00
Dan Gohman
fd3daa74c2 Generalize the zext(trunc(t) & C) instcombine to work even with
C is not a low-bits mask, and add a similar instcombine for
zext((trunc(t) & C) ^ C).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73705 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 16:30:21 +00:00
Dan Gohman
820528331f Teach ScalarEvolution how to recognize another xor(and(x, C), C) case.
If C is a single bit and the and gets analyzed as a truncate and
zero-extend, the xor can be represnted as an add.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 00:00:20 +00:00
Dan Gohman
a392c788be Instcombine zext(trunc(x) & mask) to x&mask, even if the trunc has
multiple users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73656 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 23:17:05 +00:00
Dan Gohman
559254b697 Add -disable-output to a bunch of tests that don't care about the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73633 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 20:56:26 +00:00
Dale Johannesen
42c3f554f4 This fixes a bug introduced in 72661, which can
move loads back past a check that the load address
is valid, see new testcase.  The test that went
in with 72661 has exactly this case, except that
the conditional it's moving past is checking
something else; I've settled for changing that
test to reference a global, not a pointer.  It
may be possible to scan all the tests you pass and
make sure none of them are checking any component
of the address, but it's not trivial and I'm not
trying to do that here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 20:48:23 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 18:13:58 +00:00
Eli Friedman
af79ae558f Correct an accidental duplication of the test (patch doesn't handle
creating new files very well).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73599 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 03:05:00 +00:00
Eli Friedman
a999a511f7 PR3439: Correct a silly mistake in the SimplifyDemandedUseBits code for
SRem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 02:57:36 +00:00
Dan Gohman
3034c10675 Fix ScalarEvolution's Xor handling to not assume that an And
that gets recognized with a SCEVZeroExtendExpr must be an And
with a low-bits mask. With r73540, this is no longer the case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73594 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 01:22:39 +00:00
Dale Johannesen
0ab28633c6 Test for llvm-gcc patch 73564.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 22:18:33 +00:00
Anton Korobeynikov
a4e968cb0e Make the test target-neutral
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 20:25:25 +00:00
Dan Gohman
c6ac322c1c Generalize a few more instcombines to be vector/scalar-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73541 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 19:55:29 +00:00
Dan Gohman
61ffa8e373 Instcombine's ShrinkDemandedConstant may strip bits out of constants,
obscuring what would otherwise be a low-bits mask.  Use ComputeMaskedBits
to compute what ShrinkDemandedConstant knew about to reconstruct a
low-bits mask value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 19:52:01 +00:00
Anton Korobeynikov
2932795309 GNU as refuses to assemble "pop {}" instruction. Do not emit such
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 18:49:08 +00:00
Chris Lattner
3d0cbbe0ad Testcase for r73506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 17:23:25 +00:00
Evan Cheng
67fcf56ac4 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 07:12:58 +00:00
Eli Friedman
db3c169f3a Add some generic expansion logic for SMULO and UMULO. Fixes UMULO
support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 06:58:29 +00:00
Devang Patel
c2230821a6 Use MainCU if it is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73457 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 02:09:30 +00:00
Dan Gohman
9a8c5807f8 Update this test to use fmul instead of mul.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:49:34 +00:00
Dan Gohman
6de29f8d96 Support vector casts in more places, fixing a variety of assertion
failures.

To support this, add some utility functions to Type to help support
vector/scalar-independent code. Change ConstantInt::get and
ConstantFP::get to support vector types, and add an overload to
ConstantInt::get that uses a static IntegerType type, for
convenience.

Introduce a new getConstant method for ScalarEvolution, to simplify
common use cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:12:54 +00:00
Devang Patel
11a407f43f Gracefully handle imbalanced inline function begin and end markers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:45:50 +00:00
Evan Cheng
2077e18caf ifcvt should ignore cfg where true and false successors are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:24:34 +00:00
Dale Johannesen
c1f104054d Fix the crash in this test. This is basically the same
problem addressed in 31284, but the patch there only
addressed the case where an invoke is the first thing in
a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73416 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 20:59:27 +00:00
Bill Wendling
8c3befd76e This test is failing. Revert for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 19:10:56 +00:00
Bill Wendling
f88f21c5d4 Add another testcase for r71478.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 18:36:34 +00:00
Arnold Schwaighofer
5d2c01e48a CheckTailCallReturnConstraints is missing a check on the
incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73387 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 14:43:36 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Chris Lattner
d3b295c23f fix testcase to properly check for the patch in r73195.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 05:46:02 +00:00
Dan Gohman
bd59d7b603 Implement more aggressive folding of add operand lists when
they contain multiplications of constants with add operations.
This helps simplify several kinds of things; in particular it
helps simplify expressions like ((-1 * (%a + %b)) + %a) to %b,
as expressions like this often come up in loop trip count
computations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73361 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 22:58:51 +00:00
Duncan Sands
ec08da01fc Testcase for PR4332.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73353 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 22:22:42 +00:00
Dan Gohman
4d8414f420 Teach SCEVExpander's visitAddRecExpr to reuse an existing canonical
induction variable when the addrec to be expanded does not require
a wider type. This eliminates the need for IndVarSimplify to
micro-manage SCEV expansions, because SCEVExpander now
automatically expands them in the form that IndVarSimplify considers
to be canonical. (LSR still micro-manages its SCEV expansions,
because it's optimizing for the target, rather than for
other optimizations.)

Also, this uses the new getAnyExtendExpr, which has more clever
expression simplification logic than the IndVarSimplify code it
replaces, and this cleans up some ugly expansions in code such as
the included masked-iv.ll testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73294 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 16:25:49 +00:00
Evan Cheng
e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 09:12:55 +00:00
Devang Patel
daf9e02893 llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics.
Apply defensive patch to preserve at least one lexical scope till the end of function.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73282 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 02:16:18 +00:00
Dan Gohman
0de1951a33 Adjust this test's regex strings so that they work regardless
of the target's pointer size. This avoids the need for -m32 on
the llvm-gcc command-line, which some targets may not support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 23:31:14 +00:00