Duraid Madina
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a0a11d289d
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update tablegen files - nothing to see here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24939 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-12-22 03:56:03 +00:00 |
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Chris Lattner
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0a37960d32
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these registers don't belong to any register classes, so don't mark them
as callee save. They can never be generated by the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23551 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-09-30 06:42:24 +00:00 |
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Duraid Madina
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b70c2f3ef7
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lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
care of this ourselves
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21110 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-04-06 06:18:36 +00:00 |
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Duraid Madina
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9b9d45f60e
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and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20652 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-03-17 18:17:03 +00:00 |
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