Bruno Cardoso Lopes
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9a767330f5
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Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-06-14 04:58:37 +00:00 |
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Bob Wilson
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cd70496ad1
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Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-04-19 18:11:52 +00:00 |
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Evan Cheng
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416941d50f
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Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-11-04 05:19:35 +00:00 |
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Evan Cheng
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dfed19fe2c
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Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-11-03 06:34:55 +00:00 |
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Evan Cheng
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bc7deb0f75
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Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-11-03 05:14:24 +00:00 |
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