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9a8aff0062
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18 Commits

Author SHA1 Message Date
Tim Northover
9a8aff0062 AArch64/ARM64: produce correct relocation for conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206391 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-16 15:27:52 +00:00
Tim Northover
ea9988a812 ARM64: use the integrated assembler on ELF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206378 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-16 11:52:40 +00:00
Tim Northover
2a83cb71ad AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed 
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 14:00:15 +00:00
Quentin Colombet
b980d6301f [ARM64][MC] Set the default CPU string to generic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206228 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-15 00:28:39 +00:00
Quentin Colombet
05620e5439 [ARM64][MC] Set the default CPU to cyclone when initilizating the MC layer. 
This matches that ARM64Subtarget does for now.

This is related to <rdar://problem/16573920>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206211 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-14 21:25:53 +00:00
Alp Toker
46d36be2eb Fix some doc and comment typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:47:27 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
84998a1fa9 [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:53 +00:00
Bradley Smith
01229fa891 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:27 +00:00
Bradley Smith
0fc7d2bdd2 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:16 +00:00
Bradley Smith
a5b549e03c [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:07 +00:00
Aaron Ballman
5570517bec Fixing an MSVC warning about widening the result of a 32-bit shift implicitly. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205304 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-01 12:24:25 +00:00
Aaron Ballman
103683c4cb Fixing warnings in the MSVC build. No functional changes intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-01 12:22:20 +00:00
Tim Northover
bcf0c5fd73 ARM64: uncopy/paste helper function 
It was doing functional but highly suspect operations on bools due to
the more limited shifting operands supported by memory instructions.

Should fix some MSVC warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-30 08:30:28 +00:00
Benjamin Kramer
17576b2e16 ARM64: Remove unused helper function, make others static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205112 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-29 18:00:49 +00:00
Tim Northover
7b837d8c75 ARM64: initial backend import 
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-29 10:18:08 +00:00