Tim Northover
|
1d5a2ad8a6
|
ARM64: add extra NEG pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
|
2014-04-18 14:54:35 +00:00 |
|
Matt Arsenault
|
94bdb453a4
|
Make DAGCombiner work on vector bitshifts with constant splat vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204071 91177308-0d34-0410-b5e6-96231b3b80d8
|
2014-03-17 18:58:01 +00:00 |
|
Matt Arsenault
|
53131629dc
|
Fix undefined behavior in vector shift tests.
These were all shifting the same amount as the bitwidth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203519 91177308-0d34-0410-b5e6-96231b3b80d8
|
2014-03-11 00:01:41 +00:00 |
|
Hao Liu
|
7a6f5c77c4
|
[AArch64]Fix the problems that can't select mul/add/sub of v1i8/v1i16/v1i32 types.
As this problems are similar to shl/sra/srl, also add patterns for shift nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201298 91177308-0d34-0410-b5e6-96231b3b80d8
|
2014-02-13 05:42:33 +00:00 |
|
Hao Liu
|
43ffcc571c
|
[AArch64]Can't select shift left 0 of type v1i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-12-30 02:12:46 +00:00 |
|
Hao Liu
|
dfe4fd9ceb
|
[AArch64]Add patterns to match normal shift nodes: shl, sra and srl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197969 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-12-24 09:00:21 +00:00 |
|