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153 Commits

Author SHA1 Message Date
Douglas Katzman
cd39f3c6cb [X86]: Correctly sign-extend 16-bit immediate in CALL instruction. 
Patch by Matthew Barney. Thanks!

Differential Revision: http://reviews.llvm.org/D9514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240795 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-26 16:58:59 +00:00
Douglas Katzman
a8a342bb41 [X86] Fix PR23271 - RIP-relative decoding bug in disassembler. 
Differential Revision: http://reviews.llvm.org/D9110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237310 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-13 22:44:52 +00:00
Elena Demikhovsky
d08d0340e5 AVX-512: Added all forms of FP compare instructions for KNL and SKX. 
Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236714 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-07 11:24:42 +00:00
Rafael Espindola
378981499a Fix the operand encoding in the test instruction. 
Fixes pr22995.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233686 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-31 12:31:55 +00:00
Craig Topper
a2d7ca4495 [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230924 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-02 00:22:29 +00:00
Craig Topper
f9c1605d56 [X86] Add some missing redundant MMX and SSE encodings for disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230165 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-22 07:50:41 +00:00
Craig Topper
f3455f13a2 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229078 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-13 07:42:25 +00:00
Craig Topper
e15d286e83 [X86] Add GETSEC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228514 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-07 23:36:36 +00:00
Craig Topper
0d18b852e0 [X86] Add assembler and disassembler test cases for clflushopt, clwb, pcommit, xsaves, xrstors, xsavec 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228385 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-06 06:19:28 +00:00
Craig Topper
97494e9718 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227963 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-03 11:03:57 +00:00
Craig Topper
aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:09:56 +00:00
Craig Topper
951d088ae7 [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm. 
This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226645 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 08:15:54 +00:00
Craig Topper
367b67df3e [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225432 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-08 07:41:30 +00:00
Craig Topper
f6145affbf [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. 
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-06 08:59:30 +00:00
Craig Topper
01c99892ca [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 00:00:20 +00:00
Craig Topper
71fc42dbf6 [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225075 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-02 07:02:25 +00:00
Craig Topper
c602b726a8 [X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225037 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:24:23 +00:00
Craig Topper
f8207ac705 Testcases for r224939. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224976 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 02:35:56 +00:00
Craig Topper
a996db696b [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:20:05 +00:00
Craig Topper
6eb3e3ce10 [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:19:44 +00:00
Craig Topper
654a66dbd3 Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224846 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 06:36:28 +00:00
Elena Demikhovsky
9e19cf1ffd AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220638 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-26 09:52:24 +00:00
Craig Topper
95717dbb11 [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't. 
Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present.

Fixes PR21169.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-07 07:29:50 +00:00
Adam Nemet
6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement 
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-17 17:04:56 +00:00
Adam Nemet
f36c3de849 [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields 
V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields.  This was simply not used in the decoder until now.

Fixes <rdar://problem/17402661>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-24 01:42:32 +00:00
Jim Grosbach
7ca0567652 llvm-mc: Add option for prefering hex format disassembly. 
Previously there was a separate mode entirely (--hdis vs.
--disassemble). It makes a bit more sense for the immediate printing
style to be a flag for --disassmeble rather than an entirely different
thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210700 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:26:40 +00:00
Alp Toker
8aeca44558 Reduce verbiage of lit.local.cfg files 
We can just split targets_to_build in one place and make it immutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 22:42:55 +00:00
Elena Demikhovsky
3890a42255 X86Disassembler - fixed a bug in immediate print 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-23 07:21:04 +00:00
Craig Topper
61070beae0 [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206447 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-17 06:33:45 +00:00
Craig Topper
6ee83c07a0 Test case for r204305. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204316 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 06:45:10 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 05:34:21 +00:00
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-17 10:03:43 +00:00
Craig Topper
0877c6575a Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201463 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-15 07:29:18 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:53 +00:00
David Woodhouse
a3fb0f9773 [x86] Fix 16-bit disassembly of JCXZ/JECXZ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199653 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:48 +00:00
David Woodhouse
fc19ac9654 [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSL 
The disassembler has a special case for 'L' vs. 'W' in its heuristic for
checking for 32-bit and 16-bit equivalents. We could expand the heuristic,
but better just to be consistent in using the 'L' suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199652 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:44 +00:00
David Woodhouse
d1c3f6664e [x86] Fix disassembly of callw instruction 
Not quite sure why this was marked isAsmParserOnly, but it means that the
disassembler can't see it either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199651 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:40 +00:00
David Woodhouse
7360e8caa3 [x86] Fix 16-bit handling of OpSize bit 
When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199650 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:35 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 07:36:58 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:29:32 +00:00
Craig Topper
8dff260267 Add two fp test cases I missed in my previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 23:15:19 +00:00
Craig Topper
45e6393241 Add more X86 FP stack disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 22:51:53 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 17:21:44 +00:00
Elena Demikhovsky
09a63715ce AVX-512: decoder for AVX-512, made by Alexey Bader. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 11:40:51 +00:00
Craig Topper
8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 01:42:32 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 07:19:47 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 04:28:06 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 05:17:48 +00:00
Craig Topper
6b85c4e561 Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191650 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 02:50:51 +00:00