Commit Graph

26709 Commits

Author SHA1 Message Date
Kevin Enderby
a1afbd6421 Update llvm-objdump’s Mach-O symbolizer code for Objective-C references.
This prints disassembly comments for Objective-C references to CFStrings,
Selectors, Classes and method calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 19:37:31 +00:00
Rafael Espindola
a023f50940 Cleanup this test a bit.
Use simpler names and remove unnecessary fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 19:36:21 +00:00
Rafael Espindola
c32d7489b0 Cleanup this test a bit.
Use simpler names and remove unnecessary fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 19:23:42 +00:00
David Blaikie
129ab6c6c5 DebugInfo: Simplify/tidy/correct global variable decl/def emission handling.
This fixes a bug (introduced by fixing the IR emitted from Clang where
the definition of a static member would be scoped within the class,
rather than within its lexical decl context) where the definition of a
static variable would be placed inside a class.

It also improves source fidelity by scoping static class member
definitions inside the lexical decl context in which tehy are written
(eg: namespace n { class foo { static int i; } int foo::i; } - the
definition of 'i' will be within the namespace 'n' in the DWARF output
now).

Lastly, and the original goal, this reduces debug info size slightly
(and makes debug info easier to read, etc) by placing the definitions of
non-member global variables within their namespace, rather than using a
separate namespace-scoped declaration along with a definition at global
scope.

Based on patches and discussion with Frédéric.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 19:12:43 +00:00
Rafael Espindola
b11d9944d9 Make this test a bit stricter.
This now:
* Forces the linker to include the internal definition.
* Checks the full output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 18:52:46 +00:00
Rafael Espindola
74ff8164d7 Make this test a bit stricter.
This now:
* Forces the linker to include the internal definition.
* Checks the full output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220494 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 18:44:07 +00:00
Reid Kleckner
e852ac7772 Revert "Don't count inreg params when mangling fastcall functions"
This reverts commit r214981.

I'm not sure what I was thinking when I wrote this. Testing with MSVC
shows that this function is mangled to '@f@8':
  int __fastcall f(int a, int b);

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 17:50:42 +00:00
Renato Golin
06b11e36e5 Do not emit intermediate register for zero FP immediate
This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220486 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 15:31:50 +00:00
NAKAMURA Takumi
effe629b3d Revert r220427, "[Hexagon] Adding encoding bits for add opcode."
It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 11:31:22 +00:00
Zoran Jovanovic
71832e7ed9 [mips][microMIPS] Implement ADDIUR1SP instruction
Differential Revision: http://reviews.llvm.org/D5153


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 11:13:59 +00:00
Zoran Jovanovic
fd515137bc ps][microMIPS] Implement ADDIUR2 instruction
Differential Revision: http://reviews.llvm.org/D5151


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 11:06:34 +00:00
Zoran Jovanovic
f58c95aac0 ps][microMIPS] Implement LI16 instruction
Differential Revision: http://reviews.llvm.org/D5149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 10:59:24 +00:00
Zoran Jovanovic
558236adf0 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D5774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 10:42:01 +00:00
Oliver Stannard
9982879c4e [Thumb2] Improve disassembly of memory hints
Currently, the ARM disassembler will disassemble the Thumb2 memory hint
instructions (PLD, PLDW and PLI), even for targets which do not have
these instructions. This patch adds the required checks to the
disassmebler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 08:52:58 +00:00
Akira Hatanaka
be9668675a [ARM, stack protector] If supported, use armv7 instructions.
This commit enables using movt/movw to load the stack guard address:

movw r0, :lower16:(L_g3$non_lazy_ptr-(LPC0_0+8))
movt r0, :upper16:(L_g3$non_lazy_ptr-(LPC0_0+8))
ldr r0, [pc, r0]

Previously a pc-relative load was emitted:

ldr r0, LCPI0_0
ldr r0, [pc, r0]

rdar://problem/18740489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 04:17:05 +00:00
Frederic Riss
9970b0fcaa [dwarfdump] Dump DW_AT_ranges values inline in the debug_info dump.
The output looks like that:
                      DW_AT_ranges [FORM_data4]    (0x00000000
                         [0x00000001000024a0 - 0x00000001000024c2)
                         [0x0000000100002505 - 0x000000010000268b))

Differential Revision: http://reviews.llvm.org/D5712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220466 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 04:08:34 +00:00
Peter Collingbourne
bdc3a5b99a Add llvm-go tool.
This tool lets us build LLVM components within the tree by setting up a
$GOPATH that resembles a tree fetched in the normal way with "go get".

It is intended that components such as the Go frontend will be built in-tree
using this tool.

Differential Revision: http://reviews.llvm.org/D5902

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-23 02:33:23 +00:00
Derek Schuff
5385df6bba Fix Mips nacl-mask test for new bundle-aligned label behavior
After r220439 the behavior of labels in bundle-align mode changed,
and I neglected to update this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 23:32:00 +00:00
Derek Schuff
cdb105b62f [MC] Attach labels to existing fragments instead of using a separate fragment
Summary:
Currently when emitting a label, a new data fragment is created for it if the
current fragment isn't a data fragment.
This change instead enqueues the label and attaches it to the next fragment
(e.g. created for the next instruction) if possible.

When bundle alignment is not enabled, this has no functionality change (it
just results in fewer extra fragments being created). For bundle alignment,
previously labels would point to the beginning of the bundle padding instead
of the beginning of the emitted instruction. This was not only less efficient
(e.g. jumping to the nops instead of past them) but also led to miscalculation
of the address of the GOT (since MC uses a label difference rather than
emitting a "." symbol).

Fixes https://code.google.com/p/nativeclient/issues/detail?id=3982

Test Plan: regression test attached

Reviewers: jvoung, eliben

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D5915

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220439 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 22:38:06 +00:00
Colin LeMahieu
545127f54d [Hexagon] Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.

http://reviews.llvm.org/D5624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 20:58:35 +00:00
Chad Rosier
fa16693864 [AArch64] Add support for the .inst directive.
This has been implement using the MCTargetStreamer interface as is done in the
ARM, Mips and PPC backends.

Phabricator: http://reviews.llvm.org/D5891
PR20964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220422 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 20:35:57 +00:00
Justin Bogner
6a369dbdd6 test: Make this test runnable in directories with @ in their names
Jenkins likes to use directories with names involving the '@'
character, which breaks the sed expression in this test. Switch to use
'|' on the assumption that it's less likely to show up in a path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220401 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 18:18:54 +00:00
Bill Schmidt
55321cd8a7 [PATCH] Support select-cc for VSFRC when VSX is enabled
A previous patch enabled SELECT_VSRC and SELECT_CC_VSRC for VSX to
handle <2 x double> cases.  This patch adds SELECT_VSFRC and
SELECT_CC_VSFRC to allow use of all 64 vector-scalar registers for the
f64 type when VSX is enabled.  The changes are analogous to those in
the previous patch.  I've added a new variant to vsx.ll to test the
code generation.

(I also cleaned up a little formatting in PPCInstrVSX.td from the
previous patch.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 16:58:20 +00:00
Sanjay Patel
dc18ebc4b1 Shrinkify libcalls: use float versions of double libm functions with fast-math (bug 17850)
When a call to a double-precision libm function has fast-math semantics 
(via function attribute for now because there is no IR-level FMF on calls), 
we can avoid fpext/fptrunc operations and use the float version of the call
if the input and output are both float.

We already do this optimization using a command-line option; this patch just
adds the ability for fast-math to use the existing functionality.

I moved the cl::opt from InstructionCombining into SimplifyLibCalls because
it's only ever used internally to that class.

Modified the existing test cases to use the unsafe-fp-math attribute rather
than repeating all tests.

This patch should solve: http://llvm.org/bugs/show_bug.cgi?id=17850

Differential Revision: http://reviews.llvm.org/D5893



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220390 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 15:29:23 +00:00
Diego Novillo
79ca2c234d Change error to warning when a profile cannot be found.
When the profile for a function cannot be applied, we use to emit an
error. This seems extreme. The compiler can continue, it's just that the
optimization opportunities won't include profile information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220386 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 13:36:35 +00:00
Diego Novillo
418d0cf1c1 Support using sample profiles with partial debug info.
Summary:
When using a profile, we used to require the use -gmlt so that we could
get access to the line locations. This is used to match line numbers in
the input profile to the line numbers in the function's IR.

But this is actually not necessary. The driver can provide source
location tracking without the emission of debug information. In these
cases, the annotation 'llvm.dbg.cu' is missing from the IR, but the
actual line location annotations are still present.

This patch adds a new way of looking for the start of the current
function. Instead of looking through the compile units in llvm.dbg.cu,
we can walk up the scope for the first instruction in the function with
a debug loc. If that describes the function, we use it. Otherwise, we
keep looking until we find one.

If no such instruction is found, we then give up and produce an error.

Reviewers: echristo, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5887

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220382 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 12:59:00 +00:00
Arnaud A. de Grandmaison
c9ada07cca [AArch64] Cleanup A57PBQPConstraints
And add a long awaited testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 12:40:20 +00:00
Bruno Cardoso Lopes
5165ff9878 [InstSimplify] Support constant folding to vector of pointers
ConstantFolding crashes when trying to InstSimplify the following load:

@a = private unnamed_addr constant %mst {
     i8* inttoptr (i64 -1 to i8*),
     i8* inttoptr (i64 -1 to i8*)
}, align 8

%x = load <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8

This patch fix this by adding support to this type of folding:

%x = load <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8
==> gets folded to:
  %x = <2 x i8*> <i8* inttoptr (i64 -1 to i8*), i8* inttoptr (i64 -1 to i8*)>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220380 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 12:18:48 +00:00
Jyoti Allur
8546076401 [Thumb/Thumb2] Implement restrictions on SP in register list on LDM, STM variants in thumb mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 10:41:14 +00:00
Matt Arsenault
9b0ace6364 R600/SI: Add another failing testcase for i1 copies
It's not handling phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 05:30:42 +00:00
Matt Arsenault
69643f47ad R600/SI: Add failing testcase reduced from OpenCV
This fails the verifier with:
"Expected a VCSrc_32 register, but got a VReg_1 register"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 04:26:10 +00:00
Rafael Espindola
230b53fd1b Handle spaces and quotes in file names in MRI scripts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 03:10:56 +00:00
Hans Wennborg
ec4e924836 Revert "Teach the load analysis to allow finding available values which require" (r220277)
This seems to have caused PR21330.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 23:49:52 +00:00
Lang Hames
8c4980b307 [MCJIT] Defer application of AArch64 MachO GOT relocations until resolve time.
On AArch64, GOT references are page relative (ADRP + LDR), so they can't be
applied until we know exactly where, within a page, the GOT entry will be in
the target address space.

Fixes <rdar://problem/18693976>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 23:41:15 +00:00
Rafael Espindola
f6b403a753 MRI scripts: Add addlib support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220346 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 23:18:51 +00:00
Matt Arsenault
015776f38c Add minnum / maxnum codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220342 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 23:01:01 +00:00
Matt Arsenault
252134602f Add minnum / maxnum intrinsics
These are named following the IEEE-754 names for these
functions, rather than the libm fmin / fmax to avoid
possible ambiguities. Some languages may implement something
resembling fmin / fmax which return NaN if either operand is
to propagate errors. These implement the IEEE-754 semantics
of returning the other operand if either is a NaN representing
missing data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220341 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 23:00:20 +00:00
Matt Arsenault
c68710c02d R600/SI: Add missing parameter to div_fmas intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 22:20:55 +00:00
Rafael Espindola
e539932aad Overwrite instead of adding to archives when creating them in mri scripts.
This matches the behavior of GNU ar and also makes it easier to implemnt
support for the addlib command.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 21:56:47 +00:00
Matt Arsenault
3605d74d23 R600: Use default GlobalDirective
The overridden one wasn't inserting a space,
so you would end up with .globalfoo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220329 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 21:08:36 +00:00
Arnaud A. de Grandmaison
de246de958 [PBQP] Teach PassConfig to tell if the default register allocator is used.
This enables targets to adapt their pass pipeline to the register
allocator in use. For example, with the AArch64 backend, using PBQP
with the cortex-a57, the FPLoadBalancing pass is no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220321 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 20:47:22 +00:00
Arnaud A. de Grandmaison
5eb02a6c6a [PBQP] Add a testcase for r220302: Fix coalescing benefits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220316 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 20:10:21 +00:00
David Majnemer
dea8105323 InstCombine: Simplify FoldICmpCstShrCst
This function was complicated by the fact that it tried to perform
canonicalizations that were already preformed by InstSimplify.  Remove
this extra code and move the tests over to InstSimplify.  Add asserts to
make sure our preconditions hold before we make any assumptions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220314 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 19:51:55 +00:00
Rafael Espindola
4af7ead7bd Drop support for an old version of ld64 (from darwin 9).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220310 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 18:31:09 +00:00
Rafael Espindola
33f014f298 Convert two tests to use llvm-readobj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220308 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 18:24:31 +00:00
Matt Arsenault
8287a4b564 R600/SI: Add pattern for bswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 16:25:08 +00:00
Rafael Espindola
2afb0e4d2c Add support for addmod to mri scripts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220294 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 14:46:17 +00:00
Bill Schmidt
41454cc88b [PowerPC] Avoid VSX FMA mutate when killed product reg = addend reg
With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in
the FMA mutation pass.  If we have a situation where a killed product
register is the same register as the FMA target, such as:

   %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5,
                       %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 

then the substitution makes no sense.  We end up getting a crash when
we try to extend the interval associated with the killed product
register, as there is already a live range for %vreg5 there.  This
patch just disables the mutation under those circumstances.

Since recipest.ll generates different code with VMX enabled, I've
modified that test to use -mattr=-vsx.  I've borrowed the code from
that test that exposed the bug and placed it in fma-mutate.ll, where
it tests several mutation opportunities including the "bad" one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220290 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 13:02:37 +00:00
Oliver Stannard
00e0b8a016 [ARM] NEON 32-bit scalar moves are also available in VFPv2
The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.

Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 11:49:14 +00:00
Yuri Gorshenin
7ffc5bb51a [asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an index register.
Summary: Fixed memory accesses with rbp as a base or an index register.

Reviewers: eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5819

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-21 10:22:27 +00:00