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19 Commits

Author SHA1 Message Date
Richard Osborne
8dc741e400 [XCore] Add missing 2r instructions. 
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:38:05 +00:00
Richard Osborne
763c858ede [XCore] Add TSETR instruction. 
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-17 22:32:41 +00:00
Richard Osborne
970a479c02 [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-27 22:28:30 +00:00
Richard Osborne
c47bd9899b Add instruction encodings / disassembly support for l4r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:55:32 +00:00
Richard Osborne
1f375e5bc7 Use the correct format in the STW / SETPSC instruction names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 21:25:12 +00:00
Richard Osborne
3b6a5eefe0 Add instruction encodings / disassembly support for l5r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 20:20:07 +00:00
Richard Osborne
9e6a5a3746 Add instruction encodings / disassembly support for l6r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-23 20:08:11 +00:00
Richard Osborne
9b709f8b3f Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-21 20:42:16 +00:00
Richard Osborne
b853c415c6 Add instruction encodings / disassembly support for l2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:51:15 +00:00
Richard Osborne
c78ec6b6bc Add instruction encodings / disassembly support for l3r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 18:37:49 +00:00
Richard Osborne
a68c64fbb2 Add instruction encodings / disassembler support for 2rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:22:43 +00:00
Richard Osborne
62b8786d12 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-20 17:18:47 +00:00
Richard Osborne
c47793c62c Add instruction encodings / disassembly support for l2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 16:28:02 +00:00
Richard Osborne
6e43b7f6b2 Fix parameter name in prototypes in XCoreDisassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:55:49 +00:00
Richard Osborne
35150cbf41 Add instruction encodings / disassembly support for rus instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 13:50:04 +00:00
Richard Osborne
1ffe48a84b Add instruction encodings / disassembly support for 2r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:29:31 +00:00
Richard Osborne
b4d40a04f0 Update comments to match recommended doxygen style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-17 12:13:41 +00:00
Richard Osborne
54d6266e9b Add instruction encodings and disassembly for 1r instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-16 17:37:34 +00:00
Richard Osborne
881e3cca66 Add XCore disassembler. 
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-16 17:29:14 +00:00