Bruno Cardoso Lopes
62f67f86fe
Add 256-bit load/store recognition and matching in several places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:50:58 +00:00
Benjamin Kramer
eac0796542
Don't leak operands when putting them into a shift.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:41:22 +00:00
Jim Grosbach
3b14a5c546
Update ARM Assembly of LDM/STM.
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ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:35:38 +00:00
Chris Lattner
d7c027322e
The key of a StringMap can contain nul's in it, so having first() return
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const char* doesn't make sense. Have it return StringRef instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:31:43 +00:00
Chris Lattner
154c535888
though it isn't the case here, the key of a StringMap can
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conceptually have nuls in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:21:58 +00:00
Chris Lattner
97d9730a59
add comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:12:44 +00:00
Chris Lattner
6c48244973
consolidate GlobalValue::isDeclaration into one
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non-virtual function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:10:41 +00:00
Jim Grosbach
791feea100
ARM ISB assembly parsing tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:02:25 +00:00
Chris Lattner
9854e1bebe
code cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:01:49 +00:00
Jim Grosbach
9dec507ecb
ARM ISB instruction assembly parsing.
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The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:00:31 +00:00
Benjamin Kramer
eb9a85f09e
Change Intrinsic::getDeclaration and friends to take an ArrayRef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 17:45:39 +00:00
Chris Lattner
61afc8820f
add a couple more missing C api, patch by Vitaly Lugovskiy!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 16:20:28 +00:00
Richard Osborne
c7e33965f0
Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 14:03:48 +00:00
Frits van Bommel
d155945f15
Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135145 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 11:44:09 +00:00
Nadav Rotem
d0f3ef807e
[VECTOR-SELECT]
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During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 11:11:14 +00:00
Nadav Rotem
aeb86fab3e
Add assertion for the chain value type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 10:37:54 +00:00
Jay Foad
558d3762bc
Mention all API changes I've made since 2.9 was branched.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 09:19:05 +00:00
Eric Christopher
2b88e8fbfe
Add a testcase for r135123.
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Part of rdar://9761830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 06:23:09 +00:00
Chris Lattner
d91aa14075
add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 05:53:17 +00:00
Evan Cheng
672b93a332
Unfortunately several files in MC are badly violating layering rule by using
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TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.
This patch is but one small step towards fixing this. 500 more steps to go. :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 05:43:07 +00:00
Jakob Stoklund Olesen
f1c709837b
Reapply r135121 with a fixed copy constructor.
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Original commit message:
Count references to interference cache entries.
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 05:35:11 +00:00
Devang Patel
49c19f778b
Simplify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:52:45 +00:00
Benjamin Kramer
3ff25514ce
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:38:42 +00:00
Devang Patel
d77ec6208c
Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as much as possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:14:57 +00:00
Eric Christopher
7332e6ee25
Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A
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Fixes rdar://9761830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:12:15 +00:00
Jakob Stoklund Olesen
4fcfcf4984
Revert r135121 which broke a gcc-4.2 builder.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:58:38 +00:00
Jakob Stoklund Olesen
6a9feaac93
Count references to interference cache entries.
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Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:31:14 +00:00
Eli Friedman
7e94501071
Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135120 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:22:31 +00:00
Jim Grosbach
00a66653cb
ARM tests for EOR instruction parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:22:21 +00:00
Devang Patel
0cd0c248cc
Simplify. Compile unit check inside hasValidLocation() did not add any value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:20:24 +00:00
Jim Grosbach
6a86feafa8
Remove duplicate tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:19:19 +00:00
Jim Grosbach
e77494e3e3
ARM Assembler support for DSB instruction.
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Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:18:13 +00:00
Jakob Stoklund Olesen
c66a37df73
Reapply r135074 and r135080 with a fix.
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The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.
The correct fix here is to use reference counts on the cache entries.
Coming up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:17:10 +00:00
Jim Grosbach
77f379e2a1
DMB instalias needs the same predicate as the instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135112 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:10:26 +00:00
Devang Patel
0f16a4eecc
Fix typo in DEBUG message.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:04:53 +00:00
Devang Patel
5fc0d886da
Add DEBUG messages.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:03:58 +00:00
Jim Grosbach
032434d622
ARM Assembler support for DMB instruction.
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Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:40:38 +00:00
Jim Grosbach
20fcaffaf7
Update comments. These are for assembler, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:33:10 +00:00
Owen Anderson
16884415db
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:22:26 +00:00
Bill Wendling
efe2a6557d
Add code to handle a "frameless" unwind stack.
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The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:03:31 +00:00
Jim Grosbach
6f9f884502
ARM Assembler support for DBG instruction.
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Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
53c95880f0
We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:28:55 +00:00
Jim Grosbach
14ab1c3387
ARM parsing and encoding tests for CMN/CMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:26:58 +00:00
David Greene
afd54269ab
struct Init -> class Init
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Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:25:51 +00:00
Jakob Stoklund Olesen
54c74e906a
Revert r135074 and r135080. They broke clamscan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:20:09 +00:00
Jim Grosbach
d986bc66bc
Shuffle ARM assembly tests a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:19:10 +00:00
Jim Grosbach
1cbb0c16a1
Revert 135093. Think-o.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:06:11 +00:00
Jim Grosbach
91eb0aa5de
Correct range for thumb co-processor immediate
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:03:11 +00:00
Jim Grosbach
83ab070fc1
Range checking for CDP[2] immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
466b022c99
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
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general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00