Vincent Lejeune
0c92287985
R600: 3 op instructions have no write bit but the result are store in PV
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:56:12 +00:00
Benjamin Kramer
5c35290fa3
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 17:10:37 +00:00
Vincent Lejeune
4ed9917147
R600: Relax some vector constraints on Dot4.
...
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:32 +00:00
Vincent Lejeune
25c209e9a2
R600: Some factorization
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 16:50:02 +00:00
Vincent Lejeune
152ebee8f3
R600: If previous bundle is dot4, PV valid chan is always X
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:55 +00:00
Vincent Lejeune
25f259cde2
R600: Packetize instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:27 +00:00
