Chris Lattner
3fc14c2602
Fix prolog/epilog in the presence of alloca
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5087 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 22:29:30 +00:00
Chris Lattner
27177cb1c1
Finish implementation of alias list impl
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5083 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 19:31:48 +00:00
Chris Lattner
92aec04cd6
Try #2 to get alias set stuff to work
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5077 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 16:14:51 +00:00
Chris Lattner
dfb0a541c7
Add info about register file aliasing
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5074 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 15:55:25 +00:00
Chris Lattner
f4b95d94e2
Correct the setting of Def flags on registers that are modified!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5065 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-15 22:38:47 +00:00
Chris Lattner
198ab640bb
Simplify interfaces used by regalloc to insert code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5052 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-15 20:06:35 +00:00
Misha Brukman
87e369d221
Cleaned up the code: factored out switch/case into a separate function, put
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constants in an array for quick lookup. Stole the idea from elsewhere in
Jello.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5017 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-13 12:00:06 +00:00
Misha Brukman
fa18ade05b
Treat longs as ints => pretend they're all 32-bit values and squeeze them into
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32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5008 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-13 10:43:09 +00:00
Misha Brukman
2b46e8eccc
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to
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PHI nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5001 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-13 09:54:12 +00:00
Misha Brukman
07e376bd0d
Moves now select correct opcode based on the data size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4981 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-13 04:24:53 +00:00
Misha Brukman
2adb3959f6
Implemented functions for emitting prologues and epilogues;
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removed EBP from the list of callee-saved registers (it isn't one).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4929 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-04 23:57:03 +00:00
Misha Brukman
a361c8417b
storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value
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instead of by reference, since they return the modified iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4914 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-04 17:14:13 +00:00
Misha Brukman
0af0d5bd3e
Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since
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it is target-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4911 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-04 16:47:04 +00:00
Misha Brukman
03c6fafd05
Added support for callee- and caller-save registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4897 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-03 23:11:21 +00:00
Misha Brukman
6877dd3fb0
Fix order of operands on a store from reg to [reg+offset].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4857 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-02 21:10:35 +00:00
Misha Brukman
8b938664f2
Oops. Got the MOVrm and MOVmr mixed up. Fixed. We can now print out
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instructions correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4830 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-22 23:15:27 +00:00
Misha Brukman
cf2b9ac204
Added methods to read/write values to stack in .h, fixed implementation in
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.cpp to return the iterator correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4827 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-22 22:43:47 +00:00
Misha Brukman
b83b28697c
Add definitions for function headers from MRegisterInfo.h:
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Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4784 91177308-0d34-0410-b5e6-96231b3b80d8
2002-11-20 18:59:43 +00:00
Chris Lattner
726140821f
Initial checkin of X86 backend.
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We can instruction select exactly one instruction 'ret void'. Wow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00