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ae3a0be92e
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3 Commits

Author SHA1 Message Date
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:49:04 +00:00
Dan Gohman
812d7506d0 Enable anti-dependence breaking by default when post-RA scheduling is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61078 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-16 06:21:45 +00:00
Dan Gohman
21d9003087 Initial support for anti-dependence breaking. Currently this code does not 
introduce any new spilling; it just uses unused registers.

Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59999 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-25 00:52:40 +00:00