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3 Commits

Author SHA1 Message Date
Weiming Zhao
ebcaef4340 [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForIT 
Originally, BLX was passed as operand #0 in MachineInstr and as operand
#2 in MCInst. But now, it's operand #2 in both cases.

This patch also removes unnecessary FileCheck in the test case added by r199127.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199928 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 19:55:33 +00:00
Weiming Zhao
436f2975ac Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks 
The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 18:47:54 +00:00
Evan Cheng
b16db81719 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:25:34 +00:00