Commit Graph

102163 Commits

Author SHA1 Message Date
Jim Grosbach
ab585ff20e Add iterator_ranges for block pred/succ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205603 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 02:10:59 +00:00
Jim Grosbach
93203457fc ARM: Use range-based for loops in frame lowering.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205602 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 02:10:55 +00:00
Quentin Colombet
3b2b5dfa9b [RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chance
recoloring cut-offs are encountered and register allocation failed.

This is related to PR18747

Patch by MAYUR PANDEY <mayur.p@samsung.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205601 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 02:05:21 +00:00
Quentin Colombet
cc99615837 Revert r205599, the commit was not intended to have so many changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 02:02:49 +00:00
Quentin Colombet
c65a77b92d [RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chance
recoloring cut-offs are hit.

This is related to PR18747.

Patch by MAYUR PANDEY <mayur.p@samsung.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 01:58:57 +00:00
Saleem Abdulrasool
09ebd6d735 ARM: fix test case missed in previous roundup
This should hopefully bring the last MSVC buildbot back to green!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205596 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 01:19:56 +00:00
Saleem Abdulrasool
4fd62c51b1 MIPS: remove vim swap file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205595 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 01:19:54 +00:00
Rafael Espindola
eec7d48f8e Add an assert that this is only used with .o files.
I am not sure how to get a relocation in a .dylib, but this function would
return the wrong value if passed one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 00:31:12 +00:00
Rafael Espindola
7df9059541 Implement getRelocationAddress for MachO and ET_REL elf files.
With that, fix the symbolizer to work with any ELF file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:54:35 +00:00
Rafael Espindola
5ca1f95419 Implement macho relocation iterators with section number + relocation number.
This will make it possible to implement getRelocationAddress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:51:28 +00:00
Saleem Abdulrasool
2abadea537 ARM: yet another round of ARM test clean ups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:47:24 +00:00
Jim Grosbach
91ba0a9f61 Tidy up. Space before ':' in range-based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:43:26 +00:00
Jim Grosbach
e1703660c4 Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:43:22 +00:00
Jim Grosbach
81fb6bfb85 Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:43:18 +00:00
Jim Grosbach
6cd0131b34 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:43:12 +00:00
Rafael Espindola
8cb805cf30 Fix llvm-objdump crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 23:20:02 +00:00
Rafael Espindola
67c46d286f Remove section_rel_empty. Just compare begin() and end() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 22:42:22 +00:00
Rafael Espindola
da7ea68f0d Reuse existing variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 21:48:41 +00:00
Eli Bendersky
25540a7f39 Optimize away unnecessary address casts.
Removes unnecessary casts from non-generic address spaces to the generic address
space for certain code patterns.

Patch by Jingyue Wu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 21:18:25 +00:00
Lang Hames
89218827c8 [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.
When rematerializing through truncates, the coalescer may produce instructions
with dead defs, but live implicit-defs of subregs:
E.g.
  %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32

These instructions are live, and their definitions should not be rewritten.

Fixes <rdar://problem/16492408>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:51:08 +00:00
NAKAMURA Takumi
2383986964 unconditional-branch.ll is broken for targeting x86_64-cygming. Add an explicit triple for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:40:37 +00:00
Tom Stellard
a7469745de R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4

Fixes Arithm/Absdiff.Mat/3 OpenCV test

Patch by: Bruno Jiménez

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:29 +00:00
Tom Stellard
50c16fb65c R600/SI: Lower 64-bit immediates using REG_SEQUENCE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:27 +00:00
NAKAMURA Takumi
6d394eda49 Revert r205551, "Attempt to XFAIL this on mingw and cygwin hosts." It didn't fail on cygming.
That said, it emits errors to the stderr (with exit(0));

  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205560 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:08:02 +00:00
NAKAMURA Takumi
df34283c2a llvm/test/CodeGen/X86/peephole-multiple-folds.ll: Relax expressions to satisfy win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:07:51 +00:00
Eric Christopher
f04e7df85c Attempt to XFAIL this on mingw and cygwin hosts. The line table on
these is very much off and is more than just the branch
from this bug incorrect:

Address            Line   Column File   ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x30830a0100000002      3      0      1   0             0  is_stmt
0x30830a0100000008      3      0      1   0             0  is_stmt end_sequence

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 18:23:52 +00:00
Eli Bendersky
1fcd561c73 Fix PR19270 - type mismatch caused by invalid optimization.
Patch by Jingyue Wu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205547 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 17:51:58 +00:00
Eric Christopher
1c36a6d8e7 Loosen up check so that we can pass on platforms that generate
slightly more verbose than needed line tables, e.g.:

Address            Line   Column File   ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x0000000000000000      1      0      1   0             0  is_stmt
0x0000000000000000      1      0      1   0             0  is_stmt prologue_end
0x0000000000000010      2      0      1   0             0  is_stmt
0x0000000000000018      4      0      1   0             0  is_stmt

these should probably be looked at, but it isn't affecting the correctness
of the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 17:40:08 +00:00
Saleem Abdulrasool
5fe5b3dcc8 ARM: update even more tests
More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 17:35:22 +00:00
Dmitri Gribenko
d5ba2d296e ArrayRef: use std::vector::data() now that we are building in C++11 mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205542 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 16:29:11 +00:00
Saleem Abdulrasool
27b1252c13 ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default.  This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 16:01:44 +00:00
Tim Northover
d5561bb1f0 ARM: tell LLVM about zext properties of ldrexb/ldrexh
Implementing this via ComputeMaskedBits has two advantages:
  + It actually works. DAGISel doesn't deal with the chains properly
    in the previous pattern-based solution, so they never trigger.
  + The information can be used in other DAG combines, as well as the
    trivial "get rid of truncs". For example if the trunc is in a
    different basic block.

rdar://problem/16227836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205540 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 15:10:35 +00:00
Daniel Sanders
769a6f2116 [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's
Summary:
test/MC/Mips/<isa1>/invalid-<isa2>.s
    Test that <isa1> does not support <isa2>'s instructions.
test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s
    Things that should be invalid but currently aren't. Will XPASS if any
    become invalid.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 14:14:22 +00:00
Daniel Sanders
8750f9a291 [mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205537 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 13:21:51 +00:00
Tim Northover
3eb87654a5 ARM: skip cmpxchg failure barrier if ordering is monotonic.
The terminal barrier of a cmpxchg expansion will be either Acquire or
SequentiallyConsistent. In either case it can be skipped if the
operation has Monotonic requirements on failure.

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205535 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 13:06:54 +00:00
Zoran Jovanovic
4d24300247 Implementation of 16-bit microMIPS instructions MFHI and MFLO.
Differential Revision: http://llvm-reviews.chandlerc.com/D3141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:47:34 +00:00
Daniel Sanders
8ef79fa708 [mips] Add initial (experimental) MIPS-IV support.
Summary:
Adds the 'mips4' processor and a simple test of the ELF e_flags.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I made one small change to the testcase so that it uses
mips64-unknown-linux instead of mips4-unknown-linux.

This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok
because it's supposed to be there anyway and it turns out that
FeatureCondMov is not a predicate of any instructions at the moment
(this is a bug that hasn't been noticed because there are no targets
without the conditional move instructions yet).

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3244

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:13:36 +00:00
Eric Christopher
0b6dffa018 Fix for PR 19261:
llc doesn't generate nodes for unconditional fall-through branches for targets
without FastISel implementation (X86 has it, but can be disabled by
"-fast-isel=false") in SelectionDAGBuilder::visitBr().

So for line 4 in the following testcase

1: void foo(int i){
2:   switch(i){
3:   default:
4:     break;
5:   }
6:   return;
7: }

there is no corresponding line in .debug_line section, and a debugger
cannot set a breakpoint at line 4.

Fix this by always emitting a branch when we're not optimizing and add a
testcase to ensure that there's code on every line we'd want to break.

Patch by Daniil Fukalov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:11:51 +00:00
Zoran Jovanovic
60f5dfea66 MicroMIPS specific little endian fixup data byte ordering.
Differential Revision: http://llvm-reviews.chandlerc.com/D3245


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 12:01:01 +00:00
Tim Northover
badb137729 ARM: expand atomic ldrex/strex loops in IR
The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded
at MachineInstr emission time had grown to be extremely large and
involved, to account for the subtly different code needed for the
various flavours (8/16/32/64 bit, cmpxchg/add/minmax).

Moving this transformation into the IR clears up the code
substantially, and makes future optimisations much easier:

1. an atomicrmw followed by using the *new* value can be more
   efficient. As an IR pass, simple CSE could handle this
   efficiently.
2. Making use of cmpxchg success/failure orderings only has to be done
   in one (simpler) place.
3. The common "cmpxchg; did we store?" idiom can be exposed to
   optimisation.

I intend to gradually improve this situation within the ARM backend
and make sure there are no hidden issues before moving the code out
into CodeGen to be shared with (at least ARM64/AArch64, though I think
PPC & Mips could benefit too).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 11:44:58 +00:00
Stepan Dyatkovskiy
37e5cfa4aa PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 11:29:15 +00:00
Silviu Baranga
3f11cd0d25 [ARM] When generating a vpaddl node the input lane type is not always the type of the
add operation since extract_vector_elt can perform an extend operation. Get the input lane
type from the vector on which we're performing the vpaddl operation on and extend or
truncate it to the output type of the original add node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 10:44:27 +00:00
Sasa Stankovic
10914379f6 [mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) and
%highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI
and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER
and VK_Mips_HIGHEST.

This change also deletes test file test/MC/Mips/higher_highest.ll and moves
its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s.
The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are
emitted in the .o file. Since it uses -force-mips-long-branch option, it was
created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and
R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch
started to directly calculate offsets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3230


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 10:37:45 +00:00
Tim Northover
107283d7cb ARM64: add regression test for r205519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 09:36:05 +00:00
Tim Northover
27d489f3b2 ARM64: always use i64 for the RHS of shift operations
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.

Should fix PR19294.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 09:26:16 +00:00
Oliver Stannard
b8c20fdb2b ARM: Use __STACK_LIMIT symbol for segmented stacks
We cannot use STACK_LIMIT, as it is not reserved for the compiler
by the C spec.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 08:45:16 +00:00
Andrew Trick
c8ce9677e6 Stack map docs. Remove some stray markup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 07:08:21 +00:00
Tim Northover
b642eb5dbc ARM64: don't generate __sincos_stret calls unless on MachO
This should fix PR19314.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 07:06:13 +00:00
Andrew Trick
3b8ad82b39 Minor update to the stack map documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 07:03:28 +00:00
David Blaikie
1233d41ff4 DebugInfo: Use a 64 bit type for the subrange
While we were encoding 64 bit values (data8) in the subrange itself,
using a 32 bit type for the subrange was still confusing the gdb. Oh,
and make it unsigned too.

As the comment points out, this could be pushed into the frontend so
that it would be 32 or 64 bit as appropriate, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205512 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 06:28:20 +00:00