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2 Commits

Author SHA1 Message Date
Renato Golin
0966a4e370 Adding support to LLVM for targeting Cortex-A72 
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-04 13:31:29 +00:00
Jiangning Liu
a3b8caf8a7 Implement AArch64 TTI interface isAsCheapAsAMove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214159 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-29 02:09:26 +00:00