Commit Graph

4527 Commits

Author SHA1 Message Date
David Majnemer
b99ee32499 [llvm-objdump] Print the call target next to the instruction
GNU binutils provides this behavior.  objdump -r doesn't really help
when you aren't dealing with relocation object files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241631 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:06:59 +00:00
James Y Knight
067b86fcab [Sparc] Add more instruction aliases.
These are mostly from the chart in the SparcV8 spec, section "A.3
Synthetic Instructions".

Differential Revision: http://reviews.llvm.org/D9834

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241461 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:01:07 +00:00
James Y Knight
d32974f9dc [Sparc] Add support for flush instruction.
Differential Revision: http://reviews.llvm.org/D9833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241460 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:01:04 +00:00
Asaf Badouh
169ee3383c [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale
pmulhrsw

review:
http://reviews.llvm.org/D10948

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241443 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 14:03:40 +00:00
Asaf Badouh
5047893c31 [x86][AVX512] add Multiply High Op
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241406 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 12:23:20 +00:00
Michael Kuperstein
bb803fd76e [X86] Fix incorrect/inefficient pushw encodings for x86-64 targets
Correctly support assembling "pushw $imm8" on x86-64 targets. 
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)

This fixes PR23996

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 10:25:41 +00:00
Craig Topper
9a9ee6f550 [X86] Add proper 64-bit mode checks to jrcxz and jcxz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241381 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 00:01:07 +00:00
Gabor Ballabas
4e0f6008b9 Reworking the test part of r241149
The test part of r241149 has been reverted in r241451, due to misplaced test cases.
This patch splits those test cases among the appropriate targets.

Differential Revision: http://reviews.llvm.org/D10897


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241283 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 16:53:23 +00:00
Michael Kuperstein
7edba9eec3 [X86] Convert an instruction relaxation test to use objdump instead of readobj
Patch by: david.l.kreitzer@intel.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241270 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 14:27:35 +00:00
Arnaud A. de Grandmaison
bdaa375556 [AArch64] Implement add/adds/sub/subs/cmp/cmn with negative immediate aliases
This patch teaches the AsmParser to accept add/adds/sub/subs/cmp/cmn
with a negative immediate operand and convert them as shown:

  add  Rd, Rn, -imm -> sub  Rd, Rn, imm
  sub  Rd, Rn, -imm -> add  Rd, Rn, imm
  adds Rd, Rn, -imm -> subs Rd, Rn, imm
  subs Rd, Rn, -imm -> adds Rd, Rn, imm
  cmp  Rn, -imm     -> cmn  Rn, imm
  cmn  Rn, -imm     -> cmp  Rn, imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers (gas). They are documented in the "ARMv8 Instruction Set
Overview", in the "Arithmetic (immediate)" section. This makes llvm-mc
a programmer-friendly assembler !

This also fixes PR20978: "Assembly handling of adding negative numbers
not as smart as gas".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 15:05:58 +00:00
Igor Breger
2ae30810d8 AVX-512: Implemented missing encoding for FMA scalar instructions
Added tests for encoding

Differential Revision: http://reviews.llvm.org/D10865

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241159 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 13:24:28 +00:00
Michael Kuperstein
5020a9198d [X86] Avoid over-relaxation of 8-bit immediates in integer arithmetic instructions.
Only consider an instruction a candidate for relaxation if the last operand of the 
instruction is an expression. We previously checked whether any operand is an expression,
which is useless, since for all instructions concerned, the only operand that may be
affected by relaxation is the last one.
In addition, this removes the check for having RIP as an argument, since it was 
plain wrong - even when one of the arguments is RIP, relaxation may still be needed.

This fixes PR9807.

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 10:54:42 +00:00
NAKAMURA Takumi
275fa93acf Revert part of r241149, "Fix PR23872: Integrated assembler error message when using .type directive with @ in AArch32 assembly."
The test should be split among targets. llvm/test/MC/ELF/ is assumed as X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241151 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 10:28:09 +00:00
Zoran Jovanovic
627c5342b2 [mips][microMIPS] Implement SLL and NOP instructions
http://reviews.llvm.org/D10474


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241150 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 09:54:51 +00:00
Gabor Ballabas
9f9bf86ed5 Fix PR23872: Integrated assembler error message when using .type directive with @ in AArch32 assembly.
The AArch32 assembler parses the '@' as a comment symbol, so the error message shouldn't suggest
that '@<type>' is a valid replacement when assembling for AArch32 target.

Differential Revision: http://reviews.llvm.org/D10651 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241149 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 08:58:49 +00:00
Toma Tabacu
e143a3abc2 [mips] [IAS] Add support for the .module softfloat/hardfloat directives.
These directives are used to set the default value of the SoftFloat feature.
They have the same effect as setting -m{soft, hard}-float from the command line.

Differential Revision: http://reviews.llvm.org/D9073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241066 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 13:46:03 +00:00
Toma Tabacu
dcec5265ae [mips] [IAS] Make .module directives change AssemblerOptions->front().
Differential Revision: http://reviews.llvm.org/D10643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241062 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 12:41:33 +00:00
Toma Tabacu
5dee8da754 [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives.
Differential Revision: http://reviews.llvm.org/D10657

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241052 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 09:36:50 +00:00
Elena Demikhovsky
546178bfe5 AVX-512: all forms of SCATTER instruction on SKX,
encoding, intrinsics and tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240936 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 12:14:24 +00:00
Javed Absar
263dd533ee [ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.

Reviewers: rengolin, ranjeet.singh

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:32:29 +00:00
Igor Breger
048a1eb977 AVX-512: Implemented missing encoding and intrinsics for FMA instructions
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:10:00 +00:00
Asaf Badouh
13ce163855 [x86][AVX512]
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240906 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 14:30:39 +00:00
Elena Demikhovsky
b23b2fbd3a AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240905 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 10:53:29 +00:00
Daniel Sanders
85f44d3917 [mips] Fold duplicate big-endian disassembler tests together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240887 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 17:56:44 +00:00
Daniel Sanders
279a7405e5 [mips] Sort big-endian disassembler tests by opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240885 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 16:13:59 +00:00
Daniel Sanders
44f5fc765f [mips] Make little-endian disassembler test filenames consistent.
Most are named *-el.txt. Renamed the three that were *-le.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 15:42:25 +00:00
Daniel Sanders
817cbdeae6 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 15:39:19 +00:00
Petr Hosek
bc245c01bf [MC] Ensure that pending labels are flushed when -mc-relax-all flag is used
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240870 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:54:17 +00:00
Petr Hosek
0aaf3287e3 [MC] Align fragments when -mc-relax-all flag is used
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:49:53 +00:00
Tom Stellard
4a888086a4 AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10772

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:31 +00:00
Tom Stellard
ac1a45e511 AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:07 +00:00
Douglas Katzman
cd39f3c6cb [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.
Patch by Matthew Barney. Thanks!

Differential Revision: http://reviews.llvm.org/D9514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:58:59 +00:00
Toma Tabacu
aafe2ca7d5 [mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 13:20:17 +00:00
Rafael Espindola
1de6f369b3 Diagnose undefined temporary symbols.
We already disallowed

.global .Lfoo

so this is reasonable.

This is a small cherry pick from r240130.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 20:10:45 +00:00
Rafael Espindola
b12380a76d Add a test for a recent regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 16:16:08 +00:00
Kit Barton
1ebbc68719 [PPC] Implement vmrgew and vmrgow instructions
This patch adds support for the vector merge even word and vector merge odd word
instructions introduced in POWER8.

Phabricator review: http://reviews.llvm.org/D10704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240650 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:40 +00:00
Bruno Cardoso Lopes
39b2e22f00 [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRel
Check for symbols in MCValue before using them. Bail out early in case
they are null. This fixes PR23779.

Differential Revision: http://reviews.llvm.org/D10712

rdar://problem/21532830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240649 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:23 +00:00
Toma Tabacu
e39f000353 [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.

In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().

Reviewers: dsanders, rafael

Reviewed By: dsanders, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240625 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 09:52:02 +00:00
Rafael Espindola
1e6b8f552c Don't get confused with sections whose section number is reserved.
It is perfectly possible for SHNDX to contain indexes that have the same value
as reserved st_shndx values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 14:48:54 +00:00
Zoran Jovanovic
41f28722ef [mips][microMIPS] Implement BREAK, EHB and EI instructions
http://reviews.llvm.org/D10090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 10:32:16 +00:00
Toma Tabacu
115be6213d [mips] [IAS] Add partial support for the ULHU pseudo-instruction.
Summary:
This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240410 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 14:39:42 +00:00
Petar Jovanovic
7c5bf4d38a [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 13:54:42 +00:00
Daniel Jasper
b7f5b8b4b2 Revert r240302 ("Bring r240130 back.").
This causes errors like:

  ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which
  may overflow at runtime; recompile with -fPIC
  blah.cc:function f(): error: undefined reference to ''
  blah.o:g(): error: undefined reference to ''

I have not yet come up with an appropriate reproduction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240394 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 11:31:32 +00:00
Daniel Sanders
43fab48d42 [mips] llvm-readobj can parse .MIPS.abiflags. No need to check the bytes.
Summary:

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10538


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240392 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 10:11:36 +00:00
Elena Demikhovsky
d96e362b3f AVX-512: Added all forms of VPABS instruction
Added all intrinsics, tests for encoding, tests for intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 08:19:46 +00:00
Evgeniy Stepanov
845d1a6a17 Fix PR23914.
r226830 moved the declaration of Buf to a nested scope, resulting
in a dangling reference (in StringRef Name), and a use-after-free.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240357 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 23:36:03 +00:00
Pete Cooper
54d0bc35fe Change .thumb_set to have the same error checks as .set.
According to the documentation, .thumb_set is 'the equivalent of a .set directive'.

We didn't have equivalent behaviour in terms of all the errors we could throw, for
example, when a symbol is redefined.

This change refactors parseAssignment so that it can be used by .set and .thumb_set
and implements tests for .thumb_set for all the errors thrown by that method.

Reviewed by Rafael Espíndola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240318 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 19:35:57 +00:00
Sanjoy Das
e0ef46e5e7 [FaultMaps] Add a parser for the __llvm__faultmaps section.
Summary:
The parser is exercised by llvm-objdump using -print-fault-maps.  As is
probably obvious, the code itself was "heavily inspired" by
http://reviews.llvm.org/D10434.

Reviewers: reames, atrick, JosephTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240304 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 18:03:02 +00:00
Rafael Espindola
afd779f72d Bring r240130 back.
Now that pr23900 is fixed, we can bring it back with no changes.

Original message:

Make all temporary symbols unnamed.

What this does is make all symbols that would otherwise start with a .L
(or L on MachO) unnamed.

Some of these symbols still show up in the symbol table, but we can just
make them unnamed.

In order to make sure we produce identical results when going thought assembly,
all .L (not just the compiler produced ones), are now unnamed.

Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to
205.57MB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 17:52:52 +00:00
Toma Tabacu
8204fb27ac [mips] [IAS] Add support for LAReg with identical source and destination register operands.
Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240278 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-22 13:10:23 +00:00